From patchwork Thu Jul 25 17:53:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 2833576 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 33FDD9F7D6 for ; Thu, 25 Jul 2013 17:57:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 500F6203AF for ; Thu, 25 Jul 2013 17:57:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 56A84203E1 for ; Thu, 25 Jul 2013 17:57:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757107Ab3GYRyj (ORCPT ); Thu, 25 Jul 2013 13:54:39 -0400 Received: from mail-bk0-f52.google.com ([209.85.214.52]:36270 "EHLO mail-bk0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757437Ab3GYRyg (ORCPT ); Thu, 25 Jul 2013 13:54:36 -0400 Received: by mail-bk0-f52.google.com with SMTP id mx10so809074bkb.11 for ; Thu, 25 Jul 2013 10:54:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=GoOYLQWp5xgw+LxkI/14r0xUOHYym9O6RysO6cJtv9U=; b=ZubyMf7Sxi5FIDtHDcn7eXibaGctsMH3JKPkXu47TxiMgLoibLgC7ntKuvA/4FSybj 66OMrxhHii6Zm+OVy4i7ZHMqg4NJRREQ3B0M5uAGD5ZBaOqbcwZBTogUhE7NsO7EoQAQ i2Z0WcIdeRKAmuaI99tFo+0kqob0LpXh+q4ax9zGMKWB3pjRqp+Vys5R0EMJu2Cac1+c /D3IIbBUEgtXefeI8KKpTXYNYkjDvj0yfMTSVYTkiwVvrYujCCzBSywW0SYFuqW/0Sw1 VSRCe9wAJZEa84EqlPOwf9DwQ48v4UI1rUSfbeTPeNYEUNSvGXyhezJ5XUMY0AXJMXJm YePA== X-Received: by 10.204.237.67 with SMTP id kn3mr6578124bkb.153.1374774874477; Thu, 25 Jul 2013 10:54:34 -0700 (PDT) Received: from localhost (dotsec.net. [62.75.224.215]) by mx.google.com with ESMTPSA id ct12sm11419515bkb.12.2013.07.25.10.54.30 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 25 Jul 2013 10:54:33 -0700 (PDT) From: Thierry Reding To: Bjorn Helgaas , Stephen Warren Cc: Russell King , Jason Cooper , Thomas Petazzoni , Jay Agarwal , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 09/16] PCI: tegra: set up PADS_REFCLK_CFG1 Date: Thu, 25 Jul 2013 10:53:23 -0700 Message-Id: <1374774810-18459-10-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1374774810-18459-1-git-send-email-thierry.reding@gmail.com> References: <1374774810-18459-1-git-send-email-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stephen Warren The registers PADS_REFCLK_CFG are an array of 16-bit data, one entry per PCIe root port. For Tegra30, we therefore need to write a 3rd entry in this array. Doing so mays the mini-PCIe slot on Beaver operate correctly. While we're at it, add some #defines to partially document the fields within these 16-bit values. Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding Acked-by: Bjorn Helgaas --- drivers/pci/host/pci-tegra.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 5347d7d..0c84c67 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -196,6 +196,25 @@ #define PADS_REFCLK_CFG0 0x000000C8 #define PADS_REFCLK_CFG1 0x000000CC +/* + * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit + * entries, one entry per PCIe port. These field definitions and desired + * values aren't in the TRM, but do come from NVIDIA. + */ +#define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ +#define PADS_REFCLK_CFG_E_TERM_SHIFT 7 +#define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ +#define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ + +/* Default value provided by HW engineering is 0xfa5c */ +#define PADS_REFCLK_CFG_VALUE \ + ( \ + (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ + (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ + (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ + (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ + ) + struct tegra_msi { struct msi_chip chip; DECLARE_BITMAP(used, INT_PCI_MSI_NR); @@ -809,11 +828,11 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) value |= PADS_PLL_CTL_RST_B4SM; pads_writel(pcie, value, soc->pads_pll_ctl); - /* - * Hack, set the clock voltage to the DEFAULT provided by hw folks. - * This doesn't exist in the documentation. - */ - pads_writel(pcie, 0xfa5cfa5c, PADS_REFCLK_CFG0); + /* Configure the reference clock driver */ + value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); + pads_writel(pcie, value, PADS_REFCLK_CFG0); + if (soc->num_ports > 2) + pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); /* wait for the PLL to lock */ timeout = 300;