From patchwork Thu Jul 25 17:53:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 2833570 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D8409C0319 for ; Thu, 25 Jul 2013 17:57:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A709E203AF for ; Thu, 25 Jul 2013 17:57:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 768BC2039A for ; Thu, 25 Jul 2013 17:57:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757195Ab3GYRyp (ORCPT ); Thu, 25 Jul 2013 13:54:45 -0400 Received: from mail-bk0-f41.google.com ([209.85.214.41]:47964 "EHLO mail-bk0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757011Ab3GYRym (ORCPT ); Thu, 25 Jul 2013 13:54:42 -0400 Received: by mail-bk0-f41.google.com with SMTP id jc3so815391bkc.14 for ; Thu, 25 Jul 2013 10:54:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=TKjhZtIYEF9HzP9mzAOPD7RTftf+m+BaFH9XlvNa4bc=; b=k+9umulxxyUyWhFS4bppR5lyMtt6QCWuQyzIz4u2Ki8kPEcdNht7JLARljTdt/LIgE /43E4WgOS+1VD+YQTHsSA/MALt+l8cd+1WyaZ0YlIS5syp3CHEFxgTKS+seTafOb0CUH 0gmROUh9pTPgNiRPbfw7k/uGQvyErVZnsnIfF4D2T15koaw/Myxrwg7kUqcMsCL9IMaS 8aJgjxCElHlF0my/Oeu5zpi1Dt37cZk6u6r1B2f3B4HLNcHUmn8p9UNT68492Yb32Lrq Mntwr4FrtlxQTMxf6dI4XYUghOgVrHw4PB20wX8snazO9ZiYTfWjgxXnqskjbaNEDgF8 RLXA== X-Received: by 10.204.62.201 with SMTP id y9mr6376203bkh.23.1374774880724; Thu, 25 Jul 2013 10:54:40 -0700 (PDT) Received: from localhost (dotsec.net. [62.75.224.215]) by mx.google.com with ESMTPSA id if11sm11471170bkc.15.2013.07.25.10.54.37 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 25 Jul 2013 10:54:40 -0700 (PDT) From: Thierry Reding To: Bjorn Helgaas , Stephen Warren Cc: Russell King , Jason Cooper , Thomas Petazzoni , Jay Agarwal , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 10/16] ARM: tegra: Add Tegra30 PCIe support Date: Thu, 25 Jul 2013 10:53:24 -0700 Message-Id: <1374774810-18459-11-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1374774810-18459-1-git-send-email-thierry.reding@gmail.com> References: <1374774810-18459-1-git-send-email-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Add the top-level pcie-controller node for the Tegra30 SoC. Tegra30 has three root ports that can use different lane layouts. Signed-off-by: Jay Agarwal Signed-off-by: Thierry Reding --- Changes in v5: - use symbolic constants for interrupts and clocks arch/arm/boot/dts/tegra30.dtsi | 70 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d8783f0..c8facca 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -16,6 +16,76 @@ serial4 = &uarte; }; + pcie-controller { + compatible = "nvidia,tegra30-pcie"; + device_type = "pci"; + reg = <0x00003000 0x00000800 /* PADS registers */ + 0x00003800 0x00000200 /* AFI registers */ + 0x10000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ + 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA30_CLK_PCIE>, + <&tegra_car TEGRA30_CLK_AFI>, + <&tegra_car TEGRA30_CLK_PCIEX>, + <&tegra_car TEGRA30_CLK_PLL_E>, + <&tegra_car TEGRA30_CLK_CML0>; + clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; + host1x { compatible = "nvidia,tegra30-host1x", "simple-bus"; reg = <0x50000000 0x00024000>;