From patchwork Fri Aug 9 14:49:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 2841979 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D8F139F314 for ; Fri, 9 Aug 2013 14:49:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 92B482031C for ; Fri, 9 Aug 2013 14:49:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 82E5E202CF for ; Fri, 9 Aug 2013 14:49:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933915Ab3HIOtv (ORCPT ); Fri, 9 Aug 2013 10:49:51 -0400 Received: from mail-bk0-f41.google.com ([209.85.214.41]:35978 "EHLO mail-bk0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933876Ab3HIOtu (ORCPT ); Fri, 9 Aug 2013 10:49:50 -0400 Received: by mail-bk0-f41.google.com with SMTP id na10so1117653bkb.14 for ; Fri, 09 Aug 2013 07:49:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=COFq2FFuPysH7v/mZRuaAZ04XBE80mj/lpsdWpuqHmM=; b=OZ4I/N5Ahr4772OAs/BRvAMZFLmuXczh4u3Z0nu2iSqOsaT3vam0ntUDg22FWkqMIo zILh+lHawE6MtbiqF+NZueF06/+Pn/w04L4HfMu5XcxLXbuRd+mt0uzH0xjohgmBxhYH OnzHjQFdlR9a2Mj5inD6HlJ2hLJdOPKVTWxp5CIorX9prARs1UGoGZhiyDJ09oFgcZPn TqF+Mk1W2OombUgdTVYHWz58kCsKspYr6ArnFYEb2WfH8sR3Fbq7rDI+rFnemB+uRoQj lnChtcyJcCezMD50EttLi61+WxhjiErJHEOTEUEcANRngummq2Za5Bvg184JDc89VlQb 0gBw== X-Received: by 10.205.112.198 with SMTP id et6mr2362068bkc.40.1376059788877; Fri, 09 Aug 2013 07:49:48 -0700 (PDT) Received: from localhost (port-24887.pppoe.wtnet.de. [46.59.158.238]) by mx.google.com with ESMTPSA id ps10sm3498573bkb.14.2013.08.09.07.49.47 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 09 Aug 2013 07:49:48 -0700 (PDT) From: Thierry Reding To: Stephen Warren Cc: Bjorn Helgaas , Jason Cooper , linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v6 07/14] PCI: tegra: set up PADS_REFCLK_CFG1 Date: Fri, 9 Aug 2013 16:49:25 +0200 Message-Id: <1376059772-16669-8-git-send-email-treding@nvidia.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1376059772-16669-1-git-send-email-treding@nvidia.com> References: <1376059772-16669-1-git-send-email-treding@nvidia.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Stephen Warren The registers PADS_REFCLK_CFG are an array of 16-bit data, one entry per PCIe root port. For Tegra30, we therefore need to write a 3rd entry in this array. Doing so mays the mini-PCIe slot on Beaver operate correctly. While we're at it, add some #defines to partially document the fields within these 16-bit values. Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding Acked-by: Bjorn Helgaas --- drivers/pci/host/pci-tegra.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 75607c7..ad95c40 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -195,6 +195,25 @@ #define PADS_REFCLK_CFG0 0x000000C8 #define PADS_REFCLK_CFG1 0x000000CC +/* + * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit + * entries, one entry per PCIe port. These field definitions and desired + * values aren't in the TRM, but do come from NVIDIA. + */ +#define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */ +#define PADS_REFCLK_CFG_E_TERM_SHIFT 7 +#define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ +#define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ + +/* Default value provided by HW engineering is 0xfa5c */ +#define PADS_REFCLK_CFG_VALUE \ + ( \ + (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \ + (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \ + (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \ + (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \ + ) + struct tegra_msi { struct msi_chip chip; DECLARE_BITMAP(used, INT_PCI_MSI_NR); @@ -808,11 +827,11 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) value |= PADS_PLL_CTL_RST_B4SM; pads_writel(pcie, value, soc->pads_pll_ctl); - /* - * Hack, set the clock voltage to the DEFAULT provided by hw folks. - * This doesn't exist in the documentation. - */ - pads_writel(pcie, 0xfa5cfa5c, PADS_REFCLK_CFG0); + /* Configure the reference clock driver */ + value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); + pads_writel(pcie, value, PADS_REFCLK_CFG0); + if (soc->num_ports > 2) + pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); /* wait for the PLL to lock */ timeout = 300;