From patchwork Fri Aug 9 14:49:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 2841980 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C32449F295 for ; Fri, 9 Aug 2013 14:50:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A2894202FF for ; Fri, 9 Aug 2013 14:49:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 91F0D20318 for ; Fri, 9 Aug 2013 14:49:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933930Ab3HIOtx (ORCPT ); Fri, 9 Aug 2013 10:49:53 -0400 Received: from mail-bk0-f53.google.com ([209.85.214.53]:54602 "EHLO mail-bk0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933927Ab3HIOtw (ORCPT ); Fri, 9 Aug 2013 10:49:52 -0400 Received: by mail-bk0-f53.google.com with SMTP id d7so1403980bkh.26 for ; Fri, 09 Aug 2013 07:49:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oTeLBaZwlzGXrcf3As8MzE1eOVX3mUmSSjTSqPF/Eco=; b=rxSwn6KvDA7y11DRwQnaa1q5NKNufkPnvt7pKOs9UobKSASxR4mu9ZdC9wugYY19sf tOe3ZWCLqlW7ogzrMzNJOhkIDodlYtYGHRFevlC/9fMqwE5sy757yjlZFMqxXEELpZRJ z1SZseje8xRqWiBBEWmA2ktlZ53pEXynbYZkoo/fOUY0yx58K2xoA+cAGje8T0jrNQhf vZljew3jnxzV3mK5Keagcwr5yQTK2rsaFPJrJQlACA5WGNftFUQn/OxpNJf12PvcJXyO PfTDwoScOlNkszASzQRI0wP/6auObRXAxndPfYWHZVwW4t8DVohQtCUrn+FLfbdNutP7 hx9A== X-Received: by 10.204.2.200 with SMTP id 8mr2290551bkk.92.1376059790726; Fri, 09 Aug 2013 07:49:50 -0700 (PDT) Received: from localhost (port-24887.pppoe.wtnet.de. [46.59.158.238]) by mx.google.com with ESMTPSA id 14sm2128169bkl.17.2013.08.09.07.49.49 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 09 Aug 2013 07:49:50 -0700 (PDT) From: Thierry Reding To: Stephen Warren Cc: Bjorn Helgaas , Jason Cooper , linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v6 08/14] ARM: tegra: Add Tegra30 PCIe support Date: Fri, 9 Aug 2013 16:49:26 +0200 Message-Id: <1376059772-16669-9-git-send-email-treding@nvidia.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1376059772-16669-1-git-send-email-treding@nvidia.com> References: <1376059772-16669-1-git-send-email-treding@nvidia.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the top-level pcie-controller node for the Tegra30 SoC. Tegra30 has three root ports that can use different lane layouts. Signed-off-by: Jay Agarwal Signed-off-by: Thierry Reding --- Changes in v5: - use symbolic constants for interrupts and clocks arch/arm/boot/dts/tegra30.dtsi | 70 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index d8783f0..c8facca 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -16,6 +16,76 @@ serial4 = &uarte; }; + pcie-controller { + compatible = "nvidia,tegra30-pcie"; + device_type = "pci"; + reg = <0x00003000 0x00000800 /* PADS registers */ + 0x00003800 0x00000200 /* AFI registers */ + 0x10000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ + 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ + + clocks = <&tegra_car TEGRA30_CLK_PCIE>, + <&tegra_car TEGRA30_CLK_AFI>, + <&tegra_car TEGRA30_CLK_PCIEX>, + <&tegra_car TEGRA30_CLK_PLL_E>, + <&tegra_car TEGRA30_CLK_CML0>; + clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + }; + host1x { compatible = "nvidia,tegra30-host1x", "simple-bus"; reg = <0x50000000 0x00024000>;