From patchwork Tue Sep 3 07:35:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 2853124 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 473E69F3DC for ; Tue, 3 Sep 2013 07:38:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7477A20342 for ; Tue, 3 Sep 2013 07:38:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5FAA820362 for ; Tue, 3 Sep 2013 07:38:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932657Ab3ICHia (ORCPT ); Tue, 3 Sep 2013 03:38:30 -0400 Received: from szxga01-in.huawei.com ([119.145.14.64]:38061 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932421Ab3ICHgA (ORCPT ); Tue, 3 Sep 2013 03:36:00 -0400 Received: from 172.24.2.119 (EHLO szxeml206-edg.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.4-GA FastPath queued) with ESMTP id BHQ50326; Tue, 03 Sep 2013 15:35:42 +0800 (CST) Received: from SZXEML412-HUB.china.huawei.com (10.82.67.91) by szxeml206-edg.china.huawei.com (172.24.2.59) with Microsoft SMTP Server (TLS) id 14.1.323.7; Tue, 3 Sep 2013 15:35:40 +0800 Received: from localhost (10.135.76.69) by szxeml412-hub.china.huawei.com (10.82.67.91) with Microsoft SMTP Server id 14.1.323.7; Tue, 3 Sep 2013 15:35:31 +0800 From: Yijing Wang To: Benjamin Herrenschmidt , Gavin Shan , Bjorn Helgaas , "James E.J. Bottomley" , "David S. Miller" CC: , , Yijing Wang , Hanjun Guo , Jiang Liu , Anil Gurumurthy , Vijaya Mohan Guvva , Subject: [PATCH 1/7] scsi/bfa: use pcie_capability_xxx to simplify code Date: Tue, 3 Sep 2013 15:35:09 +0800 Message-ID: <1378193715-25328-1-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.11.msysgit.1 MIME-Version: 1.0 X-Originating-IP: [10.135.76.69] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Pcie_capability_xxx() interfaces were introudced to simplify code to access PCIe Cap config space. And because PCI core saves the PCIe Cap offset in set_pcie_port_type() when device is enumerated. So we can use pci_is_pcie() instead. Signed-off-by: Yijing Wang Cc: Jiang Liu Cc: Anil Gurumurthy Cc: Vijaya Mohan Guvva Cc: "James E.J. Bottomley" Cc: linux-scsi@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- drivers/scsi/bfa/bfad.c | 9 +++------ 1 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/scsi/bfa/bfad.c b/drivers/scsi/bfa/bfad.c index 9611195..d726b81 100644 --- a/drivers/scsi/bfa/bfad.c +++ b/drivers/scsi/bfa/bfad.c @@ -767,7 +767,6 @@ bfad_pci_init(struct pci_dev *pdev, struct bfad_s *bfad) /* Adjust PCIe Maximum Read Request Size */ if (pcie_max_read_reqsz > 0) { - int pcie_cap_reg; u16 pcie_dev_ctl; u16 mask = 0xffff; @@ -794,10 +793,8 @@ bfad_pci_init(struct pci_dev *pdev, struct bfad_s *bfad) break; } - pcie_cap_reg = pci_find_capability(pdev, PCI_CAP_ID_EXP); - if (mask != 0xffff && pcie_cap_reg) { - pcie_cap_reg += 0x08; - pci_read_config_word(pdev, pcie_cap_reg, &pcie_dev_ctl); + if (mask != 0xffff && pci_is_pcie(pdev)) { + pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &pcie_dev_ctl); if ((pcie_dev_ctl & 0x7000) != mask) { printk(KERN_WARNING "BFA[%s]: " "pcie_max_read_request_size is %d, " @@ -806,7 +803,7 @@ bfad_pci_init(struct pci_dev *pdev, struct bfad_s *bfad) pcie_max_read_reqsz); pcie_dev_ctl &= ~0x7000; - pci_write_config_word(pdev, pcie_cap_reg, + pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, pcie_dev_ctl | mask); } }