From patchwork Thu Sep 5 07:55:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 2853958 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3D3479F495 for ; Thu, 5 Sep 2013 07:57:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1AFF220372 for ; Thu, 5 Sep 2013 07:57:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CF84D202FF for ; Thu, 5 Sep 2013 07:57:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1763492Ab3IEH5U (ORCPT ); Thu, 5 Sep 2013 03:57:20 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:55201 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1763476Ab3IEH5Q (ORCPT ); Thu, 5 Sep 2013 03:57:16 -0400 Received: from 172.24.2.119 (EHLO szxeml212-edg.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.4-GA FastPath queued) with ESMTP id BHC39990; Thu, 05 Sep 2013 15:57:00 +0800 (CST) Received: from SZXEML450-HUB.china.huawei.com (10.82.67.193) by szxeml212-edg.china.huawei.com (172.24.2.181) with Microsoft SMTP Server (TLS) id 14.1.323.7; Thu, 5 Sep 2013 15:56:58 +0800 Received: from localhost (10.135.76.69) by szxeml450-hub.china.huawei.com (10.82.67.193) with Microsoft SMTP Server id 14.1.323.7; Thu, 5 Sep 2013 15:56:53 +0800 From: Yijing Wang To: Benjamin Herrenschmidt , Bjorn Helgaas , "James E.J. Bottomley" CC: Gavin Shan , , , Yijing Wang , Hanjun Guo , Jiang Liu , Naresh Kumar Inna , "David S. Miller" , Jesper Juhl , Subject: [PATCH v2 2/6] scsi/csiostor: use pcie_capability_xxx to simplify code Date: Thu, 5 Sep 2013 15:55:26 +0800 Message-ID: <1378367730-25996-2-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.11.msysgit.1 In-Reply-To: <1378367730-25996-1-git-send-email-wangyijing@huawei.com> References: <1378367730-25996-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.135.76.69] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP v1->v2: add #define for Completion Timeout Value, and use pcie_capability_clear_and_set_word() instead suggested by Bjorn. Pcie_capability_xxx() interfaces were introduced to simplify code to access PCIe Cap config space. And because PCI core saves the PCIe Cap offset in set_pcie_port_type() when device is enumerated. So we can use pci_is_pcie() instead. Signed-off-by: Yijing Wang Cc: Jiang Liu Cc: "James E.J. Bottomley" Cc: Naresh Kumar Inna Cc: "David S. Miller" Cc: Jesper Juhl Cc: linux-scsi@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- drivers/scsi/csiostor/csio_hw.c | 14 +++----------- include/uapi/linux/pci_regs.h | 1 + 2 files changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/scsi/csiostor/csio_hw.c b/drivers/scsi/csiostor/csio_hw.c index 0eb35b9..07f493a 100644 --- a/drivers/scsi/csiostor/csio_hw.c +++ b/drivers/scsi/csiostor/csio_hw.c @@ -855,17 +855,9 @@ csio_hw_get_flash_params(struct csio_hw *hw) static void csio_set_pcie_completion_timeout(struct csio_hw *hw, u8 range) { - uint16_t val; - int pcie_cap; - - if (!csio_pci_capability(hw->pdev, PCI_CAP_ID_EXP, &pcie_cap)) { - pci_read_config_word(hw->pdev, - pcie_cap + PCI_EXP_DEVCTL2, &val); - val &= 0xfff0; - val |= range ; - pci_write_config_word(hw->pdev, - pcie_cap + PCI_EXP_DEVCTL2, val); - } + if (pci_is_pcie(hw->pdev)) + pcie_capability_clear_and_set_word(hw->pdev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_COMP_TIME, range); } /*****************************************************************************/ diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index baa7852..cd74182 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -558,6 +558,7 @@ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ +#define PCI_EXP_DEVCTL2_COMP_TIME 0x0f /* Completion Timeout Value */ #define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */