From patchwork Mon Dec 23 08:02:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Inamdar X-Patchwork-Id: 3396101 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 64340C0D4A for ; Mon, 23 Dec 2013 08:10:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6A0662055D for ; Mon, 23 Dec 2013 08:10:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2920320555 for ; Mon, 23 Dec 2013 08:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757002Ab3LWIKt (ORCPT ); Mon, 23 Dec 2013 03:10:49 -0500 Received: from exprod5og117.obsmtp.com ([64.18.0.149]:58210 "HELO exprod5og117.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1750730Ab3LWIKs (ORCPT ); Mon, 23 Dec 2013 03:10:48 -0500 Received: from mail-pb0-f43.google.com ([209.85.160.43]) (using TLSv1) by exprod5ob117.postini.com ([64.18.4.12]) with SMTP ID DSNKUrfwCP79/74XgHHakWgeWJ/NC1NuOSnP@postini.com; Mon, 23 Dec 2013 00:10:48 PST Received: by mail-pb0-f43.google.com with SMTP id rq2so5004383pbb.30 for ; Mon, 23 Dec 2013 00:10:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LCAa0mNjettzXV1Cnc3S2adn0Bq2aKLF/77/GAr/dAY=; b=jGnwJ6Xtvp7bFldWdbuvXFDLStRCcYI23D5VlSEzx0aqK+/w5PkDf29G9KUii/sAR8 tp+Fvl7L35vug4oVPHXAu2rUvEiFycBrwFtfGqXJ6blQES03Hvsl++Xnvz324NnHlJON b+Lo4vOS+RgAszOFNdIj7/M3hcfAkNeWGsiytK4OzJ2HgHzZ0ORMhs+4mRsbC2V+VvV2 B4oLpDuUZnsdgZIR5hJgn88M/ei22q+BfZeTRbgaPl1VpinTEDfq4Z42IHPfPXFXCgQq DBNGWwdZ4poGRN0dxfEpcDW78LQyVae5iAP9+hbwA6wK4PKocxNWeUaKYYLQahvPgi4X 4BQA== X-Received: by 10.66.141.165 with SMTP id rp5mr24406438pab.90.1387785758904; Mon, 23 Dec 2013 00:02:38 -0800 (PST) X-Gm-Message-State: ALoCoQkda6npDxg9uNdjOHDYz9RKVE3X+5llLuTDipKBOJQUn4ES2M954zO2WhxtjzE3D8H67ehpcuoLx2h5CeJgzZg1viuTolFLZUtTKMOpnsxQ1+rYYik45InCgMLyO5HukZ33yvY9eM6IlbCG2WttWWvJ15hin2Bsj5Z7w2Gc500kjYyE7Pk= X-Received: by 10.66.141.165 with SMTP id rp5mr24406421pab.90.1387785758800; Mon, 23 Dec 2013 00:02:38 -0800 (PST) Received: from pnqlab006.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id ql10sm32202966pbc.44.2013.12.23.00.02.33 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 23 Dec 2013 00:02:38 -0800 (PST) From: Tanmay Inamdar To: Bjorn Helgaas , Grant Likely , Catalin Marinas , Rob Landley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, patches@apm.com, jcm@redhat.com, Tanmay Inamdar Subject: [RFC PATCH 2/3] arm64: dts: APM X-Gene PCIe device tree nodes Date: Mon, 23 Dec 2013 13:32:03 +0530 Message-Id: <1387785725-24262-3-git-send-email-tinamdar@apm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1387785725-24262-1-git-send-email-tinamdar@apm.com> References: <1387785725-24262-1-git-send-email-tinamdar@apm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the device tree nodes for APM X-Gene PCIe controller and PCIe clock interface. Since X-Gene SOC supports maximum 5 ports, 5 dts nodes are added. Signed-off-by: Tanmay Inamdar --- arch/arm64/boot/dts/apm-mustang.dts | 4 + arch/arm64/boot/dts/apm-storm.dtsi | 140 +++++++++++++++++++++++++++++++++++ 2 files changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm-mustang.dts index 1247ca1..ab2b95f 100644 --- a/arch/arm64/boot/dts/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm-mustang.dts @@ -24,3 +24,7 @@ reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */ }; }; + +&pcie0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi index d37d736..b82f430 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi @@ -176,6 +176,146 @@ reg-names = "csr-reg"; clock-output-names = "eth8clk"; }; + + pcie0clk: pcie0clk@1f2bc000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "pcie0clk"; + reg = <0x0 0x1f2bc000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "pcie0clk"; + }; + + pcie1clk: pcie1clk@1f2cc000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "pcie1clk"; + reg = <0x0 0x1f2cc000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "pcie1clk"; + }; + + pcie2clk: pcie2clk@1f2dc000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "pcie2clk"; + reg = <0x0 0x1f2dc000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "pcie2clk"; + }; + + pcie3clk: pcie3clk@1f50c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "pcie3clk"; + reg = <0x0 0x1f50c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "pcie3clk"; + }; + + pcie4clk: pcie4clk@1f51c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "pcie4clk"; + reg = <0x0 0x1f51c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "pcie4clk"; + }; + }; + + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000>; + ranges = <0x02000000 0x0 0x00000000 0xe0 0x00000000 0x0 0x10000000 /* mem*/ + 0x01000000 0x0 0x80000000 0xe0 0x80000000 0x0 0x00010000 /* io */ + 0x00000000 0x0 0xd0000000 0xe0 0xd0000000 0x0 0x00200000 /* cfg */ + 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1>; + clocks = <&pcie0clk 0>; + clock-names = "pcieclk"; + }; + + pcie1: pcie@1f2c0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x00 0x1f2c0000 0x0 0x00010000>; + ranges = <0x02000000 0x0 0x00000000 0xd0 0x00000000 0x0 0x10000000 /* mem*/ + 0x01000000 0x0 0x80000000 0xd0 0x80000000 0x0 0x00010000 /* io */ + 0x00000000 0x0 0xd0000000 0xd0 0xd0000000 0x0 0x00200000 /* cfg */ + 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1>; + clocks = <&pcie1clk 0>; + clock-names = "pcieclk"; + }; + + pcie2: pcie@1f2d0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x00 0x1f2d0000 0x0 0x00010000>; + ranges = <0x02000000 0x0 0x00000000 0x90 0x00000000 0x0 0x10000000 /* mem*/ + 0x01000000 0x0 0x80000000 0x90 0x80000000 0x0 0x00010000 /* io */ + 0x00000000 0x0 0xd0000000 0x90 0xd0000000 0x0 0x00200000 /* cfg */ + 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1>; + clocks = <&pcie3clk 0>; + clock-names = "pcieclk"; + }; + + pcie3: pcie@1f500000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x00 0x1f500000 0x0 0x00010000>; + ranges = <0x02000000 0x0 0x00000000 0xa0 0x00000000 0x0 0x10000000 /* mem*/ + 0x01000000 0x0 0x80000000 0xa0 0x80000000 0x0 0x00010000 /* io */ + 0x00000000 0x0 0xd0000000 0xa0 0xd0000000 0x0 0x00200000 /* cfg */ + 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1>; + clocks = <&pcie3clk 0>; + clock-names = "pcieclk"; + }; + + pcie4: pcie@1f510000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x00 0x1f510000 0x0 0x00010000>; + ranges = <0x02000000 0x0 0x00000000 0xc0 0x00000000 0x0 0x10000000 /* mem*/ + 0x01000000 0x0 0x80000000 0xc0 0x80000000 0x0 0x00010000 /* io */ + 0x00000000 0x0 0xd0000000 0xc0 0xd0000000 0x0 0x00200000 /* cfg */ + 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1>; + clocks = <&pcie4clk 0>; + clock-names = "pcieclk"; }; serial0: serial@1c020000 {