From patchwork Wed Jan 8 05:02:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minghuan Lian X-Patchwork-Id: 3451641 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 38447C02DC for ; Wed, 8 Jan 2014 05:02:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 49E9B2012F for ; Wed, 8 Jan 2014 05:02:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 79FD6200D5 for ; Wed, 8 Jan 2014 05:02:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751756AbaAHFCL (ORCPT ); Wed, 8 Jan 2014 00:02:11 -0500 Received: from ch1ehsobe003.messaging.microsoft.com ([216.32.181.183]:33999 "EHLO ch1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751821AbaAHFCK (ORCPT ); Wed, 8 Jan 2014 00:02:10 -0500 Received: from mail100-ch1-R.bigfish.com (10.43.68.249) by CH1EHSOBE008.bigfish.com (10.43.70.58) with Microsoft SMTP Server id 14.1.225.22; Wed, 8 Jan 2014 05:02:09 +0000 Received: from mail100-ch1 (localhost [127.0.0.1]) by mail100-ch1-R.bigfish.com (Postfix) with ESMTP id D5D2D200B6; Wed, 8 Jan 2014 05:02:09 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: -1 X-BigFish: VS-1(zz154dIzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h17326ah8275bh8275dh1de097h186068hz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received: from mail100-ch1 (localhost.localdomain [127.0.0.1]) by mail100-ch1 (MessageSwitch) id 1389157328849381_13640; Wed, 8 Jan 2014 05:02:08 +0000 (UTC) Received: from CH1EHSMHS027.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.236]) by mail100-ch1.bigfish.com (Postfix) with ESMTP id BFD412C0071; Wed, 8 Jan 2014 05:02:08 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS027.bigfish.com (10.43.70.27) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 8 Jan 2014 05:02:08 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Wed, 8 Jan 2014 05:02:07 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.65]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s0851V2N018463; Tue, 7 Jan 2014 22:02:05 -0700 From: Minghuan Lian To: CC: Zang Roy-R61911 , Scott Wood , Kumar Gala , Bjorn Helgaas , , Minghuan Lian Subject: [PATCH 12/12][v4] pci: fsl: fix function check_pci_ctl_endpt_part Date: Wed, 8 Jan 2014 13:02:03 +0800 Message-ID: <1389157323-3088-12-git-send-email-Minghuan.Lian@freescale.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com> References: <1389157323-3088-1-git-send-email-Minghuan.Lian@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY, UNRESOLVED_TEMPLATE autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The new FSL PCI driver does not use cfg_addr of pci_controller, we may directly access PCI CCSR using fsl_pci->regs. Signed-off-by: Minghuan Lian --- change log: v4: no change v1-v3: The new patch to fix function check_pci_ctl_endpt_part Based on upstream master. Based on the discussion of RFC version here http://patchwork.ozlabs.org/patch/274487/ arch/powerpc/sysdev/fsl_pci.h | 5 ----- drivers/iommu/fsl_pamu_domain.c | 6 ++++-- include/linux/fsl/pci-common.h | 1 + 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index ae4dbe2..3176eb2 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -16,11 +16,6 @@ struct platform_device; - -/* FSL PCI controller BRR1 register */ -#define PCI_FSL_BRR1 0xbf8 -#define PCI_FSL_BRR1_VER 0xffff - extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); extern int mpc83xx_add_bridge(struct device_node *dev); u64 fsl_pci_immrbar_base(struct pci_controller *hose); diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c index c857c30..dd7bc25 100644 --- a/drivers/iommu/fsl_pamu_domain.c +++ b/drivers/iommu/fsl_pamu_domain.c @@ -36,6 +36,7 @@ #include #include +#include #include "fsl_pamu_domain.h" #include "pci.h" @@ -908,10 +909,11 @@ static struct iommu_group *get_device_iommu_group(struct device *dev) static bool check_pci_ctl_endpt_part(struct pci_controller *pci_ctl) { u32 version; + struct fsl_pci *pci = fsl_arch_sys_to_pci(pci_ctl); /* Check the PCI controller version number by readding BRR1 register */ - version = in_be32(pci_ctl->cfg_addr + (PCI_FSL_BRR1 >> 2)); - version &= PCI_FSL_BRR1_VER; + version = in_be32(&pci->regs->block_rev1); + version &= PCIE_IP_REV_MASK; /* If PCI controller version is >= 0x204 we can partition endpoints*/ if (version >= 0x204) return 1; diff --git a/include/linux/fsl/pci-common.h b/include/linux/fsl/pci-common.h index 3247682..4e4191e 100644 --- a/include/linux/fsl/pci-common.h +++ b/include/linux/fsl/pci-common.h @@ -18,6 +18,7 @@ #define PCIE_LTSSM_L0 0x16 /* L0 state */ #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */ +#define PCIE_IP_REV_MASK 0xffff #define PIWAR_EN 0x80000000 /* Enable */ #define PIWAR_PF 0x20000000 /* prefetch */ #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */