From patchwork Thu Mar 6 06:06:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Inamdar X-Patchwork-Id: 3781671 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 841159F369 for ; Thu, 6 Mar 2014 06:07:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B42C1201DD for ; Thu, 6 Mar 2014 06:07:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BE04F201E9 for ; Thu, 6 Mar 2014 06:07:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751805AbaCFGHn (ORCPT ); Thu, 6 Mar 2014 01:07:43 -0500 Received: from exprod5og102.obsmtp.com ([64.18.0.143]:46146 "HELO exprod5og102.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1750714AbaCFGG0 (ORCPT ); Thu, 6 Mar 2014 01:06:26 -0500 Received: from mail-pd0-f180.google.com ([209.85.192.180]) (using TLSv1) by exprod5ob102.postini.com ([64.18.4.12]) with SMTP ID DSNKUxgQYhMMtJmTM6Du+PTIbZruoiajYmSc@postini.com; Wed, 05 Mar 2014 22:06:26 PST Received: by mail-pd0-f180.google.com with SMTP id v10so2101219pde.11 for ; Wed, 05 Mar 2014 22:06:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oK5iTLfg6tNZ2Oh226Yqkd3pfuW2vQ9XZ3kVzLOKFro=; b=Hw3vGrm6F4JY1iZ/rQ9keAUqGYg8I7PXL3DM1SGpfKH88CKDfjcdivnJa3UVj62t5t JHvyBNtnPHisMAaJ90OIwxXJD8GcDG6bw1SbRX+i0SRaUjm0zy83j/419EkxSp4Cz5Qd cXnGAS3t7T/nirlCdTmew5n2N0WtrodfEYASq//q5ZFcNKgMDocxlYXyHsyVDqjuDNdI Mu5h6I77ca/hPu6gXBRKZtfBCdLChG8tz68/dGzXxPSWaN7QIAobLknSvgwqducI4AuN Cl6REuscUzaFkEDJvpRkwAW+L7/KQpfVUCA/kbNm97sZhzmJAPIOm8ln4J30QGsemWDs 9DKg== X-Gm-Message-State: ALoCoQnjtINvBPdFuu+I2Mp+rXC+4z8VaeSw2S+YanKCUcwB53arvszWcH4Y4eVg/pUNkX4toMKeFSLqA6F4AjFFxBMjlzGoGElhnct77YeALadqqfOc/eGFjqhvT6Uu7y7WFaMdHoVCUCH11p1y1bKZD2G4rT/CkArRawW2K0b+qvrmmWiJ/EQ= X-Received: by 10.66.158.132 with SMTP id wu4mr12288924pab.66.1394085985665; Wed, 05 Mar 2014 22:06:25 -0800 (PST) X-Received: by 10.66.158.132 with SMTP id wu4mr12288901pab.66.1394085985576; Wed, 05 Mar 2014 22:06:25 -0800 (PST) Received: from amcclab-ThinkStation-E30.amcc.com (63-147-59-2.dia.static.qwest.net. [63.147.59.2]) by mx.google.com with ESMTPSA id gg3sm15520965pbc.34.2014.03.05.22.06.23 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 05 Mar 2014 22:06:24 -0800 (PST) From: Tanmay Inamdar To: Bjorn Helgaas , Arnd Bergmann , Jason Gunthorpe , Grant Likely , Rob Herring , Catalin Marinas , Rob Landley , Liviu Dudau Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, patches@apm.com, jcm@redhat.com, Tanmay Inamdar Subject: [PATCH v4 3/4] dt-bindings: pci: xgene pcie device tree bindings Date: Wed, 5 Mar 2014 22:06:02 -0800 Message-Id: <1394085963-27553-4-git-send-email-tinamdar@apm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1394085963-27553-1-git-send-email-tinamdar@apm.com> References: <1394085963-27553-1-git-send-email-tinamdar@apm.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the bindings for X-Gene PCIe driver. The driver resides under 'drivers/pci/host/pci-xgene.c' file. Signed-off-by: Tanmay Inamdar --- .../devicetree/bindings/pci/xgene-pci.txt | 52 ++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/xgene-pci.txt diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt new file mode 100644 index 0000000..e19fdb8 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt @@ -0,0 +1,52 @@ +* AppliedMicro X-Gene PCIe interface + +Required properties: +- device_type: set to "pci" +- compatible: should contain "apm,xgene-pcie" to identify the core. +- reg: A list of physical base address and length for each set of controller + registers. Must contain an entry for each entry in the reg-names + property. +- reg-names: Must include the following entries: + "csr": controller configuration registers. + "cfg": pcie configuration space registers. +- #address-cells: set to <3> +- #size-cells: set to <2> +- ranges: ranges for the outbound memory, I/O regions. +- dma-ranges: ranges for the inbound memory regions. +- #interrupt-cells: set to <1> +- interrupt-map-mask and interrupt-map: standard PCI properties + to define the mapping of the PCIe interface to interrupt + numbers. +- clocks: from common clock binding: handle to pci clock. + +Optional properties: +- status: Either "ok" or "disabled". + +Example: + +SoC specific DT Entry: + pcie0: pcie@1f2b0000 { + status = "disabled"; + device_type = "pci"; + compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ + 0xe0 0xd0000000 0x0 0x00200000>; /* PCI config space */ + reg-names = "csr", "cfg"; + ranges = <0x01000000 0x00 0x00000000 0xe0 0x00000000 0x00 0x00010000 /* io */ + 0x02000000 0x00 0x10000000 0xe0 0x10000000 0x00 0x80000000>; /* mem */ + dma-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; + clocks = <&pcie0clk 0>; + }; + +Board specific DT Entry: + &pcie0 { + status = "ok"; + };