From patchwork Wed May 28 14:26:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 4255651 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7DE1ABF90B for ; Wed, 28 May 2014 14:27:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8267E201BB for ; Wed, 28 May 2014 14:27:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A624720173 for ; Wed, 28 May 2014 14:27:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932168AbaE1O12 (ORCPT ); Wed, 28 May 2014 10:27:28 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:33824 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754425AbaE1O0w (ORCPT ); Wed, 28 May 2014 10:26:52 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s4SEQEhf028723; Wed, 28 May 2014 09:26:14 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4SEQEsW003956; Wed, 28 May 2014 09:26:14 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 28 May 2014 09:26:14 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4SEQDhv010251; Wed, 28 May 2014 09:26:13 -0500 From: Murali Karicheri To: , , CC: Murali Karicheri , Russell King , Bjorn Helgaas , Arnd Bergmann , Jason Gunthorpe Subject: [PATCH] ARM: pci: add call to pcie_bus_configure_settings() Date: Wed, 28 May 2014 10:26:16 -0400 Message-ID: <1401287176-4986-1-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PCI core supports PCIE_BUS_SAFE and PCIE_BUS_PERFORMANCE modes. PCI controllers may not be able to handle pay load size higher than MPS and also read data size higher than MRSS. So limit the max to the least common supported payload size by calling pcie_bus_configure_settings(). Using pci=pcie_bus_safe do a walk and set the MPS to least common value used by devices on the bus. pci=pcie_bus_perf does do a walk and set MRSS to MPS. This is suggested as a better solution than pci quirk to do similar thing. Signed-off-by: Murali Karicheri CC: Russell King CC: Bjorn Helgaas CC: Arnd Bergmann CC: Jason Gunthorpe --- arch/arm/kernel/bios32.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 16d43cd..537f99e 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -545,6 +545,18 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw) */ pci_bus_add_devices(bus); } + + list_for_each_entry(sys, &head, node) { + struct pci_bus *bus = sys->bus; + + /* Configure PCI Express settings */ + if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { + struct pci_bus *child; + + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + } + } } #ifndef CONFIG_PCI_HOST_ITE8152