From patchwork Wed Jun 25 18:00:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 4422841 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3D2D4BEEAA for ; Wed, 25 Jun 2014 18:03:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6B3C320304 for ; Wed, 25 Jun 2014 18:03:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7E3032012D for ; Wed, 25 Jun 2014 18:03:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758177AbaFYSBe (ORCPT ); Wed, 25 Jun 2014 14:01:34 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:43281 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757708AbaFYSBb (ORCPT ); Wed, 25 Jun 2014 14:01:31 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s5PI0uFg027540; Wed, 25 Jun 2014 13:00:56 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5PI0u4J015224; Wed, 25 Jun 2014 13:00:56 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Wed, 25 Jun 2014 13:00:56 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5PI0XfV025950; Wed, 25 Jun 2014 13:00:51 -0500 From: Kishon Vijay Abraham I To: , , , , , , , CC: , , Rajendra Nayak , Tero Kristo , Paul Walmsley , Rob Herring , Pawel Moll , Mark Rutland , Kumar Gala , Keerthy Subject: [PATCH 4/8] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance Date: Wed, 25 Jun 2014 23:30:14 +0530 Message-ID: <1403719218-9484-5-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1403719218-9484-1-git-send-email-kishon@ti.com> References: <1403719218-9484-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are two instances of PCIe PHY in DRA7xx. So renamed optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk respectively. This is needed for adding the clocks for second PCIe PHY instance. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3ff6d7c..fe5db55 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,7 +1165,7 @@ reg = <0x021c>, <0x0220>; }; - optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { + optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; #clock-cells = <0>; @@ -1183,7 +1183,7 @@ ti,max-div = <2>; }; - optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { + optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&apll_pcie_ck>; #clock-cells = <0>; @@ -1191,7 +1191,7 @@ ti,bit-shift = <9>; }; - optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { + optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&optfclk_pciephy_div>; #clock-cells = <0>;