From patchwork Tue Aug 26 15:11:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 4782951 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 55F179F38C for ; Tue, 26 Aug 2014 15:12:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 522A020142 for ; Tue, 26 Aug 2014 15:12:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 23D7320158 for ; Tue, 26 Aug 2014 15:12:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933998AbaHZPLx (ORCPT ); Tue, 26 Aug 2014 11:11:53 -0400 Received: from mail-wg0-f45.google.com ([74.125.82.45]:38656 "EHLO mail-wg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933169AbaHZPLv (ORCPT ); Tue, 26 Aug 2014 11:11:51 -0400 Received: by mail-wg0-f45.google.com with SMTP id x12so14912984wgg.16 for ; Tue, 26 Aug 2014 08:11:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TZAO2UU+YDhSB44MxsQCeNOBDqcbg2/E/uM6l2K5eZ4=; b=P2sfxiXuSW5UPzpl9LW+Z/ULZIJpkavdHoNjS9MHnLjVvjsoGsPxukSBa8H8SBNKJM V+d3/L7wG2AzLrMsX8Ox7prxZO7HAXspmflv4WtRVdcjDHJQ/UeJCc3lRmXpza/h6ecS lGJtNPVzPox/tSXWui24Ww2ALHyaCfVHQl7bgQUM09eCj50YpEKut8+FkHDj4CNmd+0X Ryf2WqC0jhGd5XD1UV5meW+mzPL2Vyi+sUfg9U1yU6Ws6ue0Vti5nYEal1Qwy77RncAS 5zit1b/188SCnNcAL0Fj3EAbT5vGMx15XuHfQSqv6M40z1+3eybIVwaOrgPucp90Kvk9 8GXA== X-Received: by 10.180.35.134 with SMTP id h6mr22884183wij.0.1409065910099; Tue, 26 Aug 2014 08:11:50 -0700 (PDT) Received: from localhost (port-7111.pppoe.wtnet.de. [84.46.27.226]) by mx.google.com with ESMTPSA id bj4sm8991170wjc.27.2014.08.26.08.11.48 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Aug 2014 08:11:49 -0700 (PDT) From: Thierry Reding To: Bjorn Helgaas Cc: Stephen Warren , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/6] PCI: tegra: Make sure the PCIe PLL is really reset Date: Tue, 26 Aug 2014 17:11:37 +0200 Message-Id: <1409065898-26887-6-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.0.4 In-Reply-To: <1409065898-26887-1-git-send-email-thierry.reding@gmail.com> References: <1409065898-26887-1-git-send-email-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Eric Yuen Depending on the prior state of the controller, the PLL reset may not be pulsed. Clear the register bit and set it after a small delay to ensure that the PLL is really reset. Signed-off-by: Eric Yuen Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 8264bce77750..0ce43764dd36 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -849,6 +849,13 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; pads_writel(pcie, value, soc->pads_pll_ctl); + /* reset PLL */ + value = pads_readl(pcie, soc->pads_pll_ctl); + value &= ~PADS_PLL_CTL_RST_B4SM; + pads_writel(pcie, value, soc->pads_pll_ctl); + + usleep_range(20, 100); + /* take PLL out of reset */ value = pads_readl(pcie, soc->pads_pll_ctl); value |= PADS_PLL_CTL_RST_B4SM;