From patchwork Tue Sep 30 09:19:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 5001471 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0E83DBEEA6 for ; Tue, 30 Sep 2014 09:50:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 33ECF201C7 for ; Tue, 30 Sep 2014 09:50:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3A8D120172 for ; Tue, 30 Sep 2014 09:50:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752033AbaI3JuX (ORCPT ); Tue, 30 Sep 2014 05:50:23 -0400 Received: from mail-bn1on0138.outbound.protection.outlook.com ([157.56.110.138]:29664 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750945AbaI3JuW (ORCPT ); Tue, 30 Sep 2014 05:50:22 -0400 Received: from CO2PR03CA0021.namprd03.prod.outlook.com (10.141.194.148) by DM2PR03MB352.namprd03.prod.outlook.com (10.141.54.24) with Microsoft SMTP Server (TLS) id 15.0.1044.7; Tue, 30 Sep 2014 09:50:19 +0000 Received: from BY2FFO11FD031.protection.gbl (2a01:111:f400:7c0c::172) by CO2PR03CA0021.outlook.office365.com (2a01:111:e400:1414::20) with Microsoft SMTP Server (TLS) id 15.0.1039.15 via Frontend Transport; Tue, 30 Sep 2014 09:50:18 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD031.mail.protection.outlook.com (10.1.14.196) with Microsoft SMTP Server (TLS) id 15.0.1029.15 via Frontend Transport; Tue, 30 Sep 2014 09:50:18 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s8U9oEsH015564; Tue, 30 Sep 2014 02:50:14 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id C5D321AE203; Tue, 30 Sep 2014 17:19:57 +0800 (CST) From: Richard Zhu To: CC: , , , , , Richard Zhu Subject: [PATCH v4 01/10] PCI: imx6: wait the clocks to stabilize after ref_en Date: Tue, 30 Sep 2014 17:19:48 +0800 Message-ID: <1412068796-16931-2-git-send-email-r65037@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1412068796-16931-1-git-send-email-r65037@freescale.com> References: <1412068796-16931-1-git-send-email-r65037@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(199003)(189002)(16796002)(77096002)(88136002)(64706001)(6806004)(81156004)(31966008)(62966002)(33646002)(69596002)(93916002)(105586002)(45336002)(19580405001)(103686003)(19580395003)(46386002)(85852003)(92566001)(10300001)(92726001)(44976005)(80022003)(68736004)(89996001)(106466001)(87286001)(95666004)(36756003)(85306004)(21056001)(47776003)(52956003)(87936001)(46102003)(50986999)(120916001)(42186005)(4396001)(76482002)(50226001)(110136001)(77156001)(76176999)(229853001)(104166001)(2351001)(102836001)(101416001)(50466002)(97736003)(107046002)(99396003)(26826002)(20776003)(84676001)(48376002)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR03MB352; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:0; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR03MB352; X-Forefront-PRVS: 0350D7A55D Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.2) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For boards without a reset gpio we skip the delay between enabling the pcie_ref_clk and touching the RC registers for configuration. System would be hangs when the clocks are not yet settled in the DW PCIe core. So we need to make sure that there is always an appropriate delay between those two actions. Signed-off-by: Richard Zhu --- drivers/pci/host/pci-imx6.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 233fe8a..eac96fb 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) goto err_pcie; } - /* allow the clocks to stabilize */ - usleep_range(200, 500); - /* power up core phy and enable ref clock */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + /* + * the async reset input need ref clock to sync internally, + * when the ref clock comes after reset, internal synced + * reset time is too short , cannot meet the requirement. + * add one ~10us delay here. + */ + udelay(10); regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* allow the clocks to stabilize */ + usleep_range(200, 500); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0);