diff mbox

[v5,9/9] ARM: imx6sx: enable pcie on imx6sx sdb board

Message ID 1412919676-25344-10-git-send-email-richard.zhu@freescale.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Richard Zhu Oct. 10, 2014, 5:41 a.m. UTC 
From: Richard Zhu <r65037@freescale.com>

Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
---
 arch/arm/boot/dts/imx6sx-sdb.dts | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

Comments

Fabio Estevam Oct. 10, 2014, 2:50 p.m. UTC | #1 
On Fri, Oct 10, 2014 at 2:41 AM, Richard Zhu <richard.zhu@freescale.com> wrote:

> +               pinctrl_pcie: pciegrp {
> +                       fsl,pins = <
> +                               MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x17059

Why 0x17059 instead of the default 0x10b0?

> +                       >;
> +               };
> +
> +               pinctrl_pcie_reg: pciereggrp {
> +                       fsl,pins = <
> +                               MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x17059

Same here.
--
To unsubscribe from this list: send the line "unsubscribe linux-pci" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Richard Zhu Oct. 11, 2014, 8:48 a.m. UTC | #2 
> -----Original Message-----

> From: Fabio Estevam [mailto:festevam@gmail.com]

> Sent: Friday, October 10, 2014 10:51 PM

> To: Richard Zhu

> Cc: linux-pci@vger.kernel.org; Guo Shawn-R65073; Lucas Stach; Tim Harvey; Zhu

> Richard-R65037

> Subject: Re: [PATCH v5 9/9] ARM: imx6sx: enable pcie on imx6sx sdb board

> 

> On Fri, Oct 10, 2014 at 2:41 AM, Richard Zhu <richard.zhu@freescale.com> wrote:

> 

> > +               pinctrl_pcie: pciegrp {

> > +                       fsl,pins = <

> > +                               MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x17059

> 

> Why 0x17059 instead of the default 0x10b0?

[Richard] I re-use the pad cfg used by usdhc, it's would be litter faster.
Anyway, default value would be used later.
> 

> > +                       >;

> > +               };

> > +

> > +               pinctrl_pcie_reg: pciereggrp {

> > +                       fsl,pins = <

> > +                               MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x17059

> 

> Same here.

[Richard] Ok, default value would be used later.

Best Regards
Richard Zhu
diff mbox

Patch

diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index a3980d9..e538ceb 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -90,6 +90,19 @@ 
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 		};
+
+		reg_pcie: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_pcie_reg>;
+			regulator-name = "MPCIE_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 1 0>;
+			regulator-always-on;
+			enable-active-high;
+		};
 	};
 
 	sound {
@@ -251,6 +264,13 @@ 
 	};
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio2 0 0>;
+	status = "okay";
+};
+
 &ssi2 {
 	status = "okay";
 };
@@ -365,6 +385,18 @@ 
 			>;
 		};
 
+		pinctrl_pcie: pciegrp {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x17059
+			>;
+		};
+
+		pinctrl_pcie_reg: pciereggrp {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_CRS__GPIO2_IO_1	0x17059
+			>;
+		};
+
 		pinctrl_vcc_sd3: vccsd3grp {
 			fsl,pins = <
 				MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059