From patchwork Thu Oct 16 07:52:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 5088801 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D57099F30B for ; Thu, 16 Oct 2014 08:23:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CEA78201C7 for ; Thu, 16 Oct 2014 08:23:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DBF3E20176 for ; Thu, 16 Oct 2014 08:23:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751321AbaJPIXM (ORCPT ); Thu, 16 Oct 2014 04:23:12 -0400 Received: from mail-bn1bon0138.outbound.protection.outlook.com ([157.56.111.138]:18142 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750966AbaJPIXH (ORCPT ); Thu, 16 Oct 2014 04:23:07 -0400 Received: from CO2PR03CA0020.namprd03.prod.outlook.com (10.141.194.147) by DM2PR0301MB0862.namprd03.prod.outlook.com (25.160.215.148) with Microsoft SMTP Server (TLS) id 15.0.1049.19; Thu, 16 Oct 2014 08:23:04 +0000 Received: from BY2FFO11FD023.protection.gbl (2a01:111:f400:7c0c::133) by CO2PR03CA0020.outlook.office365.com (2a01:111:e400:1414::19) with Microsoft SMTP Server (TLS) id 15.0.1054.13 via Frontend Transport; Thu, 16 Oct 2014 08:23:03 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD023.mail.protection.outlook.com (10.1.15.212) with Microsoft SMTP Server (TLS) id 15.0.1039.16 via Frontend Transport; Thu, 16 Oct 2014 08:23:03 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s9G8N1v2027288; Thu, 16 Oct 2014 01:23:02 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 17EB71AE20A; Thu, 16 Oct 2014 15:52:46 +0800 (CST) From: Richard Zhu To: CC: , , , , Richard Zhu , Richard Zhu Subject: [PATCH v6 01/13] PCI: designware: Refine setup_rc and add msi data restore Date: Thu, 16 Oct 2014 15:52:31 +0800 Message-ID: <1413445963-24706-2-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1413445963-24706-1-git-send-email-richard.zhu@freescale.com> References: <1413445963-24706-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(979002)(6009001)(428002)(189002)(199003)(103686003)(68736004)(44976005)(99396003)(48376002)(69596002)(19580405001)(85852003)(95666004)(36756003)(21056001)(106466001)(31966008)(50986999)(97736003)(77096002)(76176999)(92566001)(120916001)(92726001)(93916002)(575784001)(102836001)(26826002)(84676001)(101416001)(16796002)(33646002)(19580395003)(85306004)(105586002)(77156001)(20776003)(6806004)(50466002)(2351001)(64706001)(110136001)(46102003)(80022003)(4396001)(50226001)(104166001)(81156004)(46386002)(47776003)(52956003)(107046002)(42186005)(87936001)(229853001)(89996001)(88136002)(45336002)(76482002)(87286001)(62966002)(90966001)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB0862; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0862; X-Forefront-PRVS: 036614DD9C Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.2) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Zhu - move "program correct class for RC" from dw_pcie_host_init() to dw_pcie_setup_rc(). since this is RC setup, it's better to contained in dw_pcie_setup_rc function. Then, RC can be re-setup really by dw_pcie_setup_rc(). - add one store/re-store msi cfg functions. Because that pcie controller maybe powered off during system suspend, and the msi data configuration would be lost. these functions can be used to store/restore the msi data and msi_enable during the suspend/resume callback. Signed-off-by: Richard Zhu --- drivers/pci/host/pcie-designware.c | 21 ++++++++++++++++++--- drivers/pci/host/pcie-designware.h | 3 +++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 538bbf3..b1f82ff 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -194,6 +194,19 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); } +void dw_pcie_msi_cfg_store(struct pcie_port *pp) +{ + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &pp->msi_enable); +} + +void dw_pcie_msi_cfg_restore(struct pcie_port *pp) +{ + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, + virt_to_phys((void *)pp->msi_data)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, pp->msi_enable); +} + static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) { int flag = 1; @@ -570,9 +583,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* program correct class for RC */ - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); @@ -917,6 +927,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val = memlimit | membase; dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); + /* program correct class for RC */ + dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val); + val |= PCI_CLASS_BRIDGE_PCI << 16; + dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION); + /* setup command register */ dw_pcie_readl_rc(pp, PCI_COMMAND, &val); val &= 0xffff0000; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index a476e60..b0bfed0 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -56,6 +56,7 @@ struct pcie_port { int msi_irq; struct irq_domain *irq_domain; unsigned long msi_data; + unsigned int msi_enable; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); }; @@ -83,6 +84,8 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); +void dw_pcie_msi_cfg_store(struct pcie_port *pp); +void dw_pcie_msi_cfg_restore(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp);