From patchwork Mon Oct 20 05:25:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 5102591 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 49A809FAC5 for ; Mon, 20 Oct 2014 05:55:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 52066201BB for ; Mon, 20 Oct 2014 05:55:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5CBDE201F7 for ; Mon, 20 Oct 2014 05:55:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752486AbaJTFzs (ORCPT ); Mon, 20 Oct 2014 01:55:48 -0400 Received: from mail-bl2on0143.outbound.protection.outlook.com ([65.55.169.143]:31934 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751220AbaJTFzr (ORCPT ); Mon, 20 Oct 2014 01:55:47 -0400 Received: from CH1PR03CA009.namprd03.prod.outlook.com (10.255.156.154) by DM2PR0301MB0864.namprd03.prod.outlook.com (25.160.215.15) with Microsoft SMTP Server (TLS) id 15.0.1054.13; Mon, 20 Oct 2014 05:55:44 +0000 Received: from BL2FFO11FD052.protection.gbl (10.255.156.132) by CH1PR03CA009.outlook.office365.com (10.255.156.154) with Microsoft SMTP Server (TLS) id 15.0.1054.13 via Frontend Transport; Mon, 20 Oct 2014 05:55:44 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD052.mail.protection.outlook.com (10.173.161.214) with Microsoft SMTP Server (TLS) id 15.0.1039.16 via Frontend Transport; Mon, 20 Oct 2014 05:55:44 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s9K5tbvN017261; Sun, 19 Oct 2014 22:55:38 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 82F951AE20E; Mon, 20 Oct 2014 13:25:25 +0800 (CST) From: Richard Zhu To: CC: , , , , , Richard Zhu , Richard Zhu Subject: [PATCH v8 4/9] PCI: imx6: Wait the clocks to stabilize after ref_en Date: Mon, 20 Oct 2014 13:25:19 +0800 Message-ID: <1413782724-30795-5-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1413782724-30795-1-git-send-email-richard.zhu@freescale.com> References: <1413782724-30795-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(104166001)(45336002)(46386002)(106466001)(81156004)(42186005)(4396001)(50226001)(19580405001)(44976005)(68736004)(19580395003)(62966002)(92726001)(92566001)(93916002)(84676001)(87286001)(20776003)(107046002)(2351001)(36756003)(105586002)(64706001)(120916001)(99396003)(229853001)(47776003)(77156001)(76482002)(77096002)(103686003)(95666004)(52956003)(89996001)(48376002)(85306004)(26826002)(102836001)(50466002)(85852003)(88136002)(101416001)(16796002)(31966008)(33646002)(110136001)(97736003)(6806004)(76176999)(50986999)(69596002)(21056001)(87936001)(80022003)(46102003)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB0864; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:0; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0864; X-Forefront-PRVS: 03706074BC Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.2) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Zhu For boards without a reset gpio we skip the delay between enabling the pcie_ref_clk and touching the RC registers for configuration. System would be hangs when the clocks are not yet settled in the DW PCIe core. So we need to make sure that there is always an appropriate delay between those two actions. Signed-off-by: Richard Zhu Tested-by: Tim Harvey --- drivers/pci/host/pci-imx6.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 233fe8a..eac96fb 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) goto err_pcie; } - /* allow the clocks to stabilize */ - usleep_range(200, 500); - /* power up core phy and enable ref clock */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + /* + * the async reset input need ref clock to sync internally, + * when the ref clock comes after reset, internal synced + * reset time is too short , cannot meet the requirement. + * add one ~10us delay here. + */ + udelay(10); regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* allow the clocks to stabilize */ + usleep_range(200, 500); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0);