From patchwork Fri Oct 24 02:36:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 5144031 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D5D67C11AC for ; Fri, 24 Oct 2014 03:07:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DC2692013D for ; Fri, 24 Oct 2014 03:06:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F272820160 for ; Fri, 24 Oct 2014 03:06:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751927AbaJXDG6 (ORCPT ); Thu, 23 Oct 2014 23:06:58 -0400 Received: from mail-bl2on0117.outbound.protection.outlook.com ([65.55.169.117]:58808 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751507AbaJXDG5 (ORCPT ); Thu, 23 Oct 2014 23:06:57 -0400 Received: from CH1PR03CA003.namprd03.prod.outlook.com (10.255.156.148) by BY1PR0301MB0855.namprd03.prod.outlook.com (25.160.193.149) with Microsoft SMTP Server (TLS) id 15.0.1054.13; Fri, 24 Oct 2014 03:06:55 +0000 Received: from BY2FFO11FD044.protection.gbl (10.255.156.132) by CH1PR03CA003.outlook.office365.com (10.255.156.148) with Microsoft SMTP Server (TLS) id 15.1.6.9 via Frontend Transport; Fri, 24 Oct 2014 03:06:54 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD044.mail.protection.outlook.com (10.1.14.229) with Microsoft SMTP Server (TLS) id 15.0.1049.20 via Frontend Transport; Fri, 24 Oct 2014 03:06:53 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s9O36o53009943; Thu, 23 Oct 2014 20:06:52 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1003) id 5BF0E1AE20A; Fri, 24 Oct 2014 10:36:42 +0800 (CST) From: Richard Zhu To: CC: , , , , , Richard Zhu , Richard Zhu Subject: [PATCH V2] PCI: imx6: Wait the clocks to stabilize after ref_en Date: Fri, 24 Oct 2014 10:36:40 +0800 Message-ID: <1414118200-2018-2-git-send-email-richard.zhu@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1414118200-2018-1-git-send-email-richard.zhu@freescale.com> References: <1414118200-2018-1-git-send-email-richard.zhu@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(199003)(189002)(85852003)(31966008)(16796002)(84676001)(68736004)(19580405001)(88136002)(87936001)(80022003)(19580395003)(44976005)(6806004)(87286001)(110136001)(76482002)(33646002)(89996001)(47776003)(52956003)(20776003)(64706001)(95666004)(105586002)(46102003)(2351001)(107046002)(229853001)(103686003)(106466001)(99396003)(120916001)(97736003)(26826002)(102836001)(101416001)(76176999)(50986999)(50466002)(48376002)(93916002)(92566001)(92726001)(77096002)(104166001)(85306004)(42186005)(21056001)(4396001)(50226001)(77156001)(62966002)(45336002)(46386002)(36756003)(90966001); DIR:OUT; SFP:1102; SCL:1; SRVR:BY1PR0301MB0855; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:0; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB0855; X-Forefront-PRVS: 0374433C81 Received-SPF: None (protection.outlook.com: shlinux1.ap.freescale.net does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.168.50) smtp.mailfrom=r65037@shlinux1.ap.freescale.net; X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Zhu For boards without a reset GPIO we skip the delay between enabling the pcie_ref_clk and touching the RC registers for configuration. This hangs the system if there isn't a proper delay to ensure the clocks are settled in the DW PCIe core. Also iMX6Q always needs an additional 10us delay to make sure the reset is propagated through the core, as we don't have an explicitly controlled reset input on this SoC. Signed-off-by: Richard Zhu Tested-by: Tim Harvey Tested-by: Fabio Estevam Signed-off-by: Lucas Stach Acked-by: Lucas Stach Tested-by: Fabio Estevam --- drivers/pci/host/pci-imx6.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 233fe8a..eac96fb 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) goto err_pcie; } - /* allow the clocks to stabilize */ - usleep_range(200, 500); - /* power up core phy and enable ref clock */ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + /* + * the async reset input need ref clock to sync internally, + * when the ref clock comes after reset, internal synced + * reset time is too short , cannot meet the requirement. + * add one ~10us delay here. + */ + udelay(10); regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* allow the clocks to stabilize */ + usleep_range(200, 500); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0);