From patchwork Mon Oct 27 13:22:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 5160241 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4B8009F318 for ; Mon, 27 Oct 2014 12:44:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 52B302035B for ; Mon, 27 Oct 2014 12:44:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6D7172027D for ; Mon, 27 Oct 2014 12:44:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752999AbaJ0MmB (ORCPT ); Mon, 27 Oct 2014 08:42:01 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:28142 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752694AbaJ0Mlm (ORCPT ); Mon, 27 Oct 2014 08:41:42 -0400 Received: from 172.24.2.119 (EHLO szxeml404-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CBJ49247; Mon, 27 Oct 2014 20:41:39 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml404-hub.china.huawei.com (10.82.67.59) with Microsoft SMTP Server id 14.3.158.1; Mon, 27 Oct 2014 20:41:31 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , , Thomas Gleixner , Konrad Rzeszutek Wilk , , Joerg Roedel , , , "Benjamin Herrenschmidt" , , , Sebastian Ott , "Tony Luck" , , "David S. Miller" , , Chris Metcalf , Ralf Baechle , Lucas Stach , David Vrabel , "Sergei Shtylyov" , Michael Ellerman , Thierry Reding , "Thomas Petazzoni" , Yijing Wang Subject: [PATCH 12/16] arm/iop13xx/MSI: Use MSI controller framework to configure MSI/MSI-X irq Date: Mon, 27 Oct 2014 21:22:18 +0800 Message-ID: <1414416142-31239-13-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1414416142-31239-1-git-send-email-wangyijing@huawei.com> References: <1414416142-31239-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use MSI controller framework instead of arch MSI functions to configure MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework. Signed-off-by: Yijing Wang --- arch/arm/mach-iop13xx/include/mach/pci.h | 4 ++++ arch/arm/mach-iop13xx/iq81340mc.c | 3 +++ arch/arm/mach-iop13xx/iq81340sc.c | 5 ++++- arch/arm/mach-iop13xx/msi.c | 11 +++++++++-- 4 files changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-iop13xx/include/mach/pci.h b/arch/arm/mach-iop13xx/include/mach/pci.h index 59f42b5..c8f5caf 100644 --- a/arch/arm/mach-iop13xx/include/mach/pci.h +++ b/arch/arm/mach-iop13xx/include/mach/pci.h @@ -11,6 +11,10 @@ void iop13xx_atu_select(struct hw_pci *plat_pci); void iop13xx_pci_init(void); void iop13xx_map_pci_memory(void); +#ifdef CONFIG_PCI_MSI +extern struct msi_controller iop13xx_msi_ctrl; +#endif + #define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \ PCI_STATUS_SIG_TARGET_ABORT | \ PCI_STATUS_REC_TARGET_ABORT | \ diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index 9cd07d3..7b802f5 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -59,6 +59,9 @@ static struct hw_pci iq81340mc_pci __initdata = { .map_irq = iq81340mc_pcix_map_irq, .scan = iop13xx_scan_bus, .preinit = iop13xx_pci_init, +#ifdef CONFIG_PCI_MSI + .msi_ctrl = &iop13xx_msi_ctrl, +#endif }; static int __init iq81340mc_pci_init(void) diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index b3ec11c..934de2e 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -60,7 +60,10 @@ static struct hw_pci iq81340sc_pci __initdata = { .setup = iop13xx_pci_setup, .scan = iop13xx_scan_bus, .map_irq = iq81340sc_atux_map_irq, - .preinit = iop13xx_pci_init + .preinit = iop13xx_pci_init, +#ifdef CONFIG_PCI_MSI + .msi_ctrl = &iop13xx_msi_ctrl, +#endif }; static int __init iq81340sc_pci_init(void) diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index e7730cf..07a512e 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c @@ -132,7 +132,8 @@ static struct irq_chip iop13xx_msi_chip = { .irq_unmask = unmask_msi_irq, }; -int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +static int iop13xx_setup_msi_irq(struct msi_controller *ctrl, + struct pci_dev *dev, struct msi_desc *desc) { int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1); struct msi_msg msg; @@ -159,7 +160,13 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) return 0; } -void arch_teardown_msi_irq(unsigned int irq) +static void iop13xx_teardown_msi_irq(struct msi_controller *ctrl, + unsigned int irq) { irq_free_desc(irq); } + +struct msi_controller iop13xx_msi_ctrl = { + .setup_irq = iop13xx_setup_msi_irq, + .teardown_irq = iop13xx_teardown_msi_irq, +};