From patchwork Wed Nov 5 01:07:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chuansheng Liu X-Patchwork-Id: 5231641 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BF685C11AC for ; Wed, 5 Nov 2014 01:24:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EFD9A20173 for ; Wed, 5 Nov 2014 01:24:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1F03820120 for ; Wed, 5 Nov 2014 01:24:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752067AbaKEBYx (ORCPT ); Tue, 4 Nov 2014 20:24:53 -0500 Received: from mga02.intel.com ([134.134.136.20]:43268 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751303AbaKEBYx (ORCPT ); Tue, 4 Nov 2014 20:24:53 -0500 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 04 Nov 2014 17:24:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,316,1413270000"; d="scan'208";a="602412350" Received: from shsibuild003.sh.intel.com ([10.239.147.159]) by orsmga001.jf.intel.com with ESMTP; 04 Nov 2014 17:24:50 -0800 From: Chuansheng Liu To: bhelgaas@google.com, aaron.lu@intel.com, tj@kernel.org, rjw@rjwysocki.net, mister.freeman@laposte.net Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, chuansheng.liu@intel.com Subject: [PATCH] PCI: Do not enable async suspend for JMicron chips Date: Wed, 5 Nov 2014 09:07:45 +0800 Message-Id: <1415149665-26669-1-git-send-email-chuansheng.liu@intel.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The JMicron chip 361/363/368 contains one SATA controller and one PATA controller, they are brother-relation ship in PCI tree, but for powering on these both controller, we must follow the sequence one by one, otherwise one of them can not be powered on successfully. So here we disable the async suspend method for Jmicron chip. Cc: stable@vger.kernel.org # 3.15+ Signed-off-by: Chuansheng Liu --- drivers/pci/pci.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 625a4ac..53128f0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2046,7 +2046,17 @@ void pci_pm_init(struct pci_dev *dev) pm_runtime_forbid(&dev->dev); pm_runtime_set_active(&dev->dev); pm_runtime_enable(&dev->dev); - device_enable_async_suspend(&dev->dev); + + /* + * The JMicron chip 361/363/368 contains one SATA controller and + * one PATA controller, they are brother-relation ship in PCI tree, + * but for powering on these both controller, we must follow the + * sequence one by one, otherwise one of them can not be powered on + * successfully, so here we disable the async suspend method for + * Jmicron chip. + */ + if (dev->vendor != PCI_VENDOR_ID_JMICRON) + device_enable_async_suspend(&dev->dev); dev->wakeup_prepared = false; dev->pm_cap = 0;