From patchwork Wed Apr 15 09:49:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minghuan Lian X-Patchwork-Id: 6219461 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C1B679F2EC for ; Wed, 15 Apr 2015 09:47:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CC04E202E9 for ; Wed, 15 Apr 2015 09:47:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0825820376 for ; Wed, 15 Apr 2015 09:47:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753583AbbDOJrk (ORCPT ); Wed, 15 Apr 2015 05:47:40 -0400 Received: from mail-bn1bon0113.outbound.protection.outlook.com ([157.56.111.113]:57436 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752210AbbDOJrj (ORCPT ); Wed, 15 Apr 2015 05:47:39 -0400 Received: from CH1PR03CA011.namprd03.prod.outlook.com (10.255.156.156) by BN3PR03MB1480.namprd03.prod.outlook.com (0.163.35.143) with Microsoft SMTP Server (TLS) id 15.1.136.25; Wed, 15 Apr 2015 09:47:37 +0000 Received: from BN1BFFO11FD040.protection.gbl (10.255.156.132) by CH1PR03CA011.outlook.office365.com (10.255.156.156) with Microsoft SMTP Server (TLS) id 15.1.130.23 via Frontend Transport; Wed, 15 Apr 2015 09:47:37 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD040.mail.protection.outlook.com (10.58.144.103) with Microsoft SMTP Server (TLS) id 15.1.142.12 via Frontend Transport; Wed, 15 Apr 2015 09:47:37 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.53]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t3F9lRx9007250; Wed, 15 Apr 2015 02:47:34 -0700 From: Minghuan Lian To: CC: , Zang Roy-R61911 , Hu Mingkai-B21284 , Scott Wood , Yoder Stuart-B08248 , Arnd Bergmann , Bjorn Helgaas , "Minghuan Lian" Subject: [PATCH 2/2] pci/layerscape: Add LS2085A MSI support Date: Wed, 15 Apr 2015 17:49:24 +0800 Message-ID: <1429091364-31939-3-git-send-email-Minghuan.Lian@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1429091364-31939-1-git-send-email-Minghuan.Lian@freescale.com> References: <1429091364-31939-1-git-send-email-Minghuan.Lian@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(199003)(189002)(106466001)(47776003)(76176999)(50986999)(50226001)(46102003)(2351001)(104016003)(19580405001)(110136001)(6806004)(229853001)(19580395003)(62966003)(77156002)(87936001)(48376002)(86362001)(36756003)(50466002)(77096005)(2950100001)(105606002)(92566002)(85426001)(4001430100001)(19627235001); DIR:OUT; SFP:1102; SCL:1; SRVR:BN3PR03MB1480; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1480; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002010)(5005006); SRVR:BN3PR03MB1480; BCL:0; PCL:0; RULEID:; SRVR:BN3PR03MB1480; X-Forefront-PRVS: 0547116B72 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2015 09:47:37.3921 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB1480 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Freescale LS2085A uses GICv3 ITS to provide MSI functionality, but it only supports 64 isolation context identifiers. So, all the PCIe devices inserted to the same PCIe controller will share the fixed ICID. Signed-off-by: Minghuan Lian --- Depend on pci-layerscape-Add-LS2085A-PCIe-support.patch drivers/pci/host/pci-layerscape.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 15c5e47..1f317ca 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -30,20 +30,38 @@ /* PEX LUT registers */ #define PCIE_LUT_BASE 0x80000 +#define PCIE_LUT_PEXLCR 0x024 /* PEX LUT Control Register */ +#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) +#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) +#define PCIE_LUT_MASK_ALL 0xffff +#define PCIE_LUT_DR_NUM 32 +#define PCIE_LUT_ENABLE (0x1 << 31) #define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug register */ #define PCIE_ATU_NUM 6 +#define PCIE_MSI_MAX_NUM 64 +#define PCIE_ICID_BASE 1 + struct ls_pcie { struct dw_pcie_port pp; void __iomem *regs; void __iomem *lut; struct regmap *scfg; int index; + int icid; }; #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) +void arch_msi_share_devid_update(struct pci_dev *pdev, u32 *dev_id, u32 *nvesc) +{ + struct ls_pcie *pcie = to_ls_pcie(pdev->bus->sysdata); + + *dev_id = pcie->icid; + *nvesc = PCIE_MSI_MAX_NUM; +} + static int ls1_pcie_link_up(struct dw_pcie_port *pp) { struct ls_pcie *pcie = to_ls_pcie(pp); @@ -136,6 +154,12 @@ static int ls2_pcie_host_init(struct dw_pcie_port *pp) dw_pcie_dbi_write(pp, val, PCI_HEADER_TYPE & ~0x3); dw_pcie_dbi_write(pp, 0, PCIE_DBI_RO_WR_EN); + /* Set LUT. All request ID will map to a static ICID */ + iowrite32(pcie->icid, pcie->lut + PCIE_LUT_PEXLCR); + iowrite32(PCIE_LUT_MASK_ALL, pcie->lut + PCIE_LUT_UDR(0)); + iowrite32(PCIE_LUT_ENABLE | pcie->icid, + pcie->lut + PCIE_LUT_LDR(0)); + if (!ls2_pcie_link_up(pp)) dev_err(pp->dev, "phy link never came up\n"); @@ -159,6 +183,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev) const struct of_device_id *match; struct ls_pcie *pcie; struct resource *res; + static int ls_pcie_num; int ret; match = of_match_device(ls_pcie_of_match, &pdev->dev); @@ -177,6 +202,8 @@ static int __init ls_pcie_probe(struct platform_device *pdev) } pcie->lut = pcie->regs + PCIE_LUT_BASE; + pcie->index = ls_pcie_num++; + pcie->icid = PCIE_ICID_BASE + pcie->index; pcie->pp.dev = &pdev->dev; pcie->pp.dbi = pcie->regs; pcie->pp.dw_ops = (struct dw_host_ops *)match->data;