From patchwork Fri May 1 06:02:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 6308281 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D09BE9F387 for ; Fri, 1 May 2015 06:04:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D0A4E203E6 for ; Fri, 1 May 2015 06:04:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD421203E9 for ; Fri, 1 May 2015 06:04:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753329AbbEAGEP (ORCPT ); Fri, 1 May 2015 02:04:15 -0400 Received: from e23smtp03.au.ibm.com ([202.81.31.145]:60520 "EHLO e23smtp03.au.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752268AbbEAGEM (ORCPT ); Fri, 1 May 2015 02:04:12 -0400 Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 1 May 2015 16:04:10 +1000 Received: from d23dlp03.au.ibm.com (202.81.31.214) by e23smtp03.au.ibm.com (202.81.31.209) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 1 May 2015 16:04:09 +1000 Received: from d23relay08.au.ibm.com (d23relay08.au.ibm.com [9.185.71.33]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 171D8357804C for ; Fri, 1 May 2015 16:04:09 +1000 (EST) Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t41640KL45416544 for ; Fri, 1 May 2015 16:04:08 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t4163YLT005540 for ; Fri, 1 May 2015 16:03:35 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t4163YlP005123; Fri, 1 May 2015 16:03:34 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.253.15]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 6D19EA0272; Fri, 1 May 2015 16:03:11 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 1DBF416AA05; Fri, 1 May 2015 16:03:11 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id E14799421E6; Fri, 1 May 2015 16:03:10 +1000 (AEST) From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org, benh@kernel.crashing.org, bhelgaas@google.com, Gavin Shan Subject: [PATCH v4 02/21] powerpc/powernv: Enable M64 on P7IOC Date: Fri, 1 May 2015 16:02:49 +1000 Message-Id: <1430460188-31343-3-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1430460188-31343-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1430460188-31343-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15050106-0009-0000-0000-000001533D97 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch enables M64 window on P7IOC, which has been enabled on PHB3. Comparing to PHB3, there are 16 M64 BARs and each of them are divided to 8 segments. So each PHB can support 128 M64 segments. Also, P7IOC has M64DT, which helps mapping one particular M64 segment# to arbitrary PE#. However, we just provide 128 M64 (16 BARs) segments and fixed mapping between PE# and M64 segment# in order to keep same logic to support M64 for PHB3 and P7IOC. In turn, we just need different phb->init_m64() hooks for P7IOC and PHB3. Signed-off-by: Gavin Shan --- arch/powerpc/platforms/powernv/pci-ioda.c | 115 ++++++++++++++++++++++++++---- 1 file changed, 103 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index f8bc950..646962f 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -165,6 +165,67 @@ static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe) clear_bit(pe, phb->ioda.pe_alloc); } +static int pnv_ioda1_init_m64(struct pnv_phb *phb) +{ + struct resource *r; + int seg; + s64 rc; + + /* Each PHB supports 16 separate M64 BARs, each of which are + * divided into 8 segments. So there are number of M64 segments + * as total PE#, which is 128. + */ + for (seg = 0; seg < phb->ioda.total_pe; seg += 8) { + unsigned long base; + + base = phb->ioda.m64_base + seg * phb->ioda.m64_segsize; + rc = opal_pci_set_phb_mem_window(phb->opal_id, + OPAL_M64_WINDOW_TYPE, + seg / 8, + base, + 0, /* unused */ + 8 * phb->ioda.m64_segsize); + if (rc != OPAL_SUCCESS) { + pr_warn(" Failure %lld configuring M64 BAR#%d on PHB#%d\n", + rc, seg / 8, phb->hose->global_number); + goto fail; + } + + rc = opal_pci_phb_mmio_enable(phb->opal_id, + OPAL_M64_WINDOW_TYPE, + seg / 8, + OPAL_ENABLE_M64_SPLIT); + if (rc != OPAL_SUCCESS) { + pr_warn(" Failure %lld enabling M64 BAR#%d on PHB#%d\n", + rc, seg / 8, phb->hose->global_number); + goto fail; + } + } + + /* Strip of the segment used by the reserved PE, which + * is expected to be 0 or last supported PE# + */ + r = &phb->hose->mem_resources[1]; + if (phb->ioda.reserved_pe == 0) + r->start += phb->ioda.m64_segsize; + else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1)) + r->end -= phb->ioda.m64_segsize; + else + pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", + phb->ioda.reserved_pe); + + return 0; + +fail: + for ( ; seg >= 0; seg -= 8) + opal_pci_phb_mmio_enable(phb->opal_id, + OPAL_M64_WINDOW_TYPE, + seg / 8, + OPAL_DISABLE_M64); + + return -EIO; +} + /* The default M64 BAR is shared by all PEs */ static int pnv_ioda2_init_m64(struct pnv_phb *phb) { @@ -222,7 +283,7 @@ fail: return -EIO; } -static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb) +static void pnv_ioda_reserve_m64_pe(struct pnv_phb *phb) { resource_size_t sgsz = phb->ioda.m64_segsize; struct pci_dev *pdev; @@ -248,8 +309,8 @@ static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb) } } -static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb, - struct pci_bus *bus, int all) +static int pnv_ioda_pick_m64_pe(struct pnv_phb *phb, + struct pci_bus *bus, int all) { resource_size_t segsz = phb->ioda.m64_segsize; struct pci_dev *pdev; @@ -346,6 +407,28 @@ done: pe->master = master_pe; list_add_tail(&pe->list, &master_pe->slaves); } + + /* P7IOC supports M64DT, which helps mapping M64 segment + * to one particular PE#. Unfortunately, PHB3 has fixed + * mapping between M64 segment and PE#. In order for same + * logic for P7IOC and PHB3, we enforce fixed mapping + * between M64 segment and PE# on P7IOC. + */ + if (phb->type == PNV_PHB_IODA1) { + int64_t rc; + + rc = opal_pci_map_pe_mmio_window(phb->opal_id, + pe->pe_number, + OPAL_M64_WINDOW_TYPE, + pe->pe_number / 8, + pe->pe_number % 8); + if (rc != OPAL_SUCCESS) + pr_warn("%s: Failure %lld mapping " + "M64 for PHB#%d-PE#%d\n", + __func__, rc, + phb->hose->global_number, + pe->pe_number); + } } kfree(pe_alloc); @@ -360,12 +443,6 @@ static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) const u32 *r; u64 pci_addr; - /* FIXME: Support M64 for P7IOC */ - if (phb->type != PNV_PHB_IODA2) { - pr_info(" Not support M64 window\n"); - return; - } - if (!firmware_has_feature(FW_FEATURE_OPALv3)) { pr_info(" Firmware too old to support M64 window\n"); return; @@ -394,9 +471,23 @@ static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) /* Use last M64 BAR to cover M64 window */ phb->ioda.m64_bar_idx = 15; - phb->init_m64 = pnv_ioda2_init_m64; - phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe; - phb->pick_m64_pe = pnv_ioda2_pick_m64_pe; + phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; + phb->pick_m64_pe = pnv_ioda_pick_m64_pe; + switch (phb->type) { + case PNV_PHB_IODA1: + phb->init_m64 = pnv_ioda1_init_m64; + break; + case PNV_PHB_IODA2: + phb->init_m64 = pnv_ioda2_init_m64; + break; + default: + phb->init_m64 = NULL; + phb->reserve_m64_pe = NULL; + phb->pick_m64_pe = NULL; + phb->ioda.m64_size = 0; + phb->ioda.m64_segsize = 0; + phb->ioda.m64_base = 0; + } } static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)