From patchwork Thu May 21 07:05:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 6452541 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4BFB5C0432 for ; Thu, 21 May 2015 07:09:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6E8312044B for ; Thu, 21 May 2015 07:09:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 626752041A for ; Thu, 21 May 2015 07:09:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932090AbbEUHJl (ORCPT ); Thu, 21 May 2015 03:09:41 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:4173 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754846AbbEUHJb (ORCPT ); Thu, 21 May 2015 03:09:31 -0400 Received: from 172.24.2.119 (EHLO szxeml428-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CLR80590; Thu, 21 May 2015 15:09:20 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml428-hub.china.huawei.com (10.82.67.183) with Microsoft SMTP Server id 14.3.158.1; Thu, 21 May 2015 15:09:10 +0800 From: Yijing Wang To: CC: , , , , Yijing Wang Subject: [PATCH v4 3/3] PCI: Use pdev->has_secondary_link to identify pcie link Date: Thu, 21 May 2015 15:05:04 +0800 Message-ID: <1432191904-16451-3-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1432191904-16451-1-git-send-email-wangyijing@huawei.com> References: <1432191904-16451-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We assumed pcie root port and downstream port always have pcie link, but in some unusual pcie topology platform like ATCA, it may has the following pcie tree: root port ---- downstream port -----upstream port | |downstream port Now we introduce a flag pdev->has_secondary_link to tag a device whether has pcie link, use it instead. Signed-off-by: Yijing Wang --- drivers/pci/pcie/aer/aerdrv_core.c | 3 +-- drivers/pci/probe.c | 2 +- drivers/pci/vc.c | 3 +-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index 5653ea9..9803e3d 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c @@ -425,8 +425,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev) if (driver && driver->reset_link) { status = driver->reset_link(udev); - } else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM || - pci_pcie_type(udev) == PCI_EXP_TYPE_ROOT_PORT) { + } else if (udev->has_secondary_link) { status = default_reset_link(udev); } else { dev_printk(KERN_DEBUG, &dev->dev, diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 192c6b9..eba4928 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1645,7 +1645,7 @@ static int only_one_child(struct pci_bus *bus) return 0; if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT) return 1; - if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM && + if (parent->has_secondary_link && !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) return 1; return 0; diff --git a/drivers/pci/vc.c b/drivers/pci/vc.c index 7e1304d..dfbab61 100644 --- a/drivers/pci/vc.c +++ b/drivers/pci/vc.c @@ -108,8 +108,7 @@ static void pci_vc_enable(struct pci_dev *dev, int pos, int res) struct pci_dev *link = NULL; /* Enable VCs from the downstream device */ - if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || - pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) + if (!dev->has_secondary_link) return; ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);