From patchwork Thu Jun 4 06:41:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 6544331 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AF0359F6CE for ; Thu, 4 Jun 2015 06:45:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C361E2074E for ; Thu, 4 Jun 2015 06:45:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B68062075F for ; Thu, 4 Jun 2015 06:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751737AbbFDGpG (ORCPT ); Thu, 4 Jun 2015 02:45:06 -0400 Received: from e23smtp01.au.ibm.com ([202.81.31.143]:38741 "EHLO e23smtp01.au.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752680AbbFDGpD (ORCPT ); Thu, 4 Jun 2015 02:45:03 -0400 Received: from /spool/local by e23smtp01.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jun 2015 16:45:00 +1000 Received: from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id A3F2F2BB0052; Thu, 4 Jun 2015 16:44:59 +1000 (EST) Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t546hbTC41615368; Thu, 4 Jun 2015 16:43:45 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t546hB0u002965; Thu, 4 Jun 2015 16:43:12 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t546hBbB002494; Thu, 4 Jun 2015 16:43:11 +1000 Received: from bran.ozlabs.ibm.com (unknown [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 49F8DA03E1; Thu, 4 Jun 2015 16:42:26 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 5477FE387C; Thu, 4 Jun 2015 16:42:26 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id 43E329422B2; Thu, 4 Jun 2015 16:42:26 +1000 (AEST) From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, benh@kernel.crashing.org, bhelgaas@google.com, aik@ozlabs.ru, panto@antoniou-consulting.com, robherring2@gmail.com, grant.likely@linaro.org, Gavin Shan Subject: [PATCH v5 09/42] powerpc/powernv: pnv_ioda_setup_dma() configure one PE only Date: Thu, 4 Jun 2015 16:41:38 +1000 Message-Id: <1433400131-18429-10-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1433400131-18429-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1433400131-18429-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15060406-1618-0000-0000-000002355625 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The original implementation of pnv_ioda_setup_dma() iterates the list of PEs and configures the DMA32 space for them one by one. The function was designed to be called during PHB fixup time. When configuring PE's DMA32 space in pcibios_setup_bridge(), in order to support PCI hotplug, we have to have the function PE oriented. The patch introduces one more argument "struct pnv_ioda_pe *pe" to pnv_ioda_setup_dma(). The caller, pnv_pci_ioda_setup_DMA(), gets PE from the list and passes to it. The patch shouldn't cause logic changes. Signed-off-by: Gavin Shan --- v5: * Split from PATCH[v4 06/21] --- arch/powerpc/platforms/powernv/pci-ioda.c | 60 ++++++++++++++----------------- 1 file changed, 27 insertions(+), 33 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 4af3d06..63fad4d 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -2558,12 +2558,14 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, pnv_ioda_setup_bus_dma(pe, pe->pbus); } -static void pnv_ioda_setup_dma(struct pnv_phb *phb) +static void pnv_ioda_setup_dma(struct pnv_phb *phb, struct pnv_ioda_pe *pe) { struct pci_controller *hose = phb->hose; - struct pnv_ioda_pe *pe; unsigned int dma_weight; + if (!pe->dma32_weight) + return; + /* Calculate the PHB's DMA weight */ dma_weight = pnv_ioda_phb_dma_weight(phb); pr_info("PCI%04x has %ld DMA32 segments, total weight %d\n", @@ -2571,38 +2573,28 @@ static void pnv_ioda_setup_dma(struct pnv_phb *phb) pnv_pci_ioda_setup_opal_tce_kill(phb); - /* Walk our PE list and configure their DMA segments, hand them - * out one base segment plus any residual segments based on - * weight + /* + * For IODA2 compliant PHB3, we needn't care about the weight. + * The all available 32-bits DMA space will be assigned to + * the specific PE. */ - list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { - if (!pe->dma32_weight) - continue; + if (phb->type == PNV_PHB_IODA1) { + unsigned int segs, base = 0; - /* - * For IODA2 compliant PHB3, we needn't care about the weight. - * The all available 32-bits DMA space will be assigned to - * the specific PE. - */ - if (phb->type == PNV_PHB_IODA1) { - unsigned int segs, base = 0; - - if (pe->dma32_weight < - dma_weight / phb->ioda.dma32_segcount) - segs = 1; - else - segs = (pe->dma32_weight * - phb->ioda.dma32_segcount) / dma_weight; - - pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", - pe->dma32_weight, segs); - pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); + if (pe->dma32_weight < + dma_weight / phb->ioda.dma32_segcount) + segs = 1; + else + segs = (pe->dma32_weight * + phb->ioda.dma32_segcount) / dma_weight; - base += segs; - } else { - pe_info(pe, "Assign DMA32 space\n"); - pnv_pci_ioda2_setup_dma_pe(phb, pe); - } + pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", + pe->dma32_weight, segs); + pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); + base += segs; + } else { + pe_info(pe, "Assign DMA32 space\n"); + pnv_pci_ioda2_setup_dma_pe(phb, pe); } } @@ -3073,12 +3065,14 @@ static void pnv_pci_ioda_setup_DMA(void) { struct pci_controller *hose, *tmp; struct pnv_phb *phb; + struct pnv_ioda_pe *pe; list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { - pnv_ioda_setup_dma(hose->private_data); + phb = hose->private_data; + list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) + pnv_ioda_setup_dma(phb, pe); /* Mark the PHB initialization done */ - phb = hose->private_data; phb->initialized = 1; } }