From patchwork Thu Jun 4 06:41:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 6544171 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4E8109F326 for ; Thu, 4 Jun 2015 06:44:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0869A20755 for ; Thu, 4 Jun 2015 06:44:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DDFA420760 for ; Thu, 4 Jun 2015 06:44:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752650AbbFDGoI (ORCPT ); Thu, 4 Jun 2015 02:44:08 -0400 Received: from e23smtp01.au.ibm.com ([202.81.31.143]:38521 "EHLO e23smtp01.au.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752584AbbFDGnt (ORCPT ); Thu, 4 Jun 2015 02:43:49 -0400 Received: from /spool/local by e23smtp01.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jun 2015 16:43:46 +1000 Received: from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id 8C0C42BB0052; Thu, 4 Jun 2015 16:43:45 +1000 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t546hbnm46530628; Thu, 4 Jun 2015 16:43:45 +1000 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t546hBF1014041; Thu, 4 Jun 2015 16:43:13 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t546hBBD013514; Thu, 4 Jun 2015 16:43:11 +1000 Received: from bran.ozlabs.ibm.com (unknown [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id B2009A03E2; Thu, 4 Jun 2015 16:42:26 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id BD2BAE387C; Thu, 4 Jun 2015 16:42:26 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id AC6759422B2; Thu, 4 Jun 2015 16:42:26 +1000 (AEST) From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, benh@kernel.crashing.org, bhelgaas@google.com, aik@ozlabs.ru, panto@antoniou-consulting.com, robherring2@gmail.com, grant.likely@linaro.org, Gavin Shan Subject: [PATCH v5 10/42] powerpc/powernv: Trace DMA32 segments consumed by PE Date: Thu, 4 Jun 2015 16:41:39 +1000 Message-Id: <1433400131-18429-11-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1433400131-18429-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1433400131-18429-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15060406-1618-0000-0000-0000023555AF Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On P7IOC, the whole DMA32 space is divided evenly to 256MB segments. Each PE can consume one or multiple DMA32 segments. Current code doesn't trace the available DMA32 segments and those consumed by one particular PE. It's conflicting with PCI hotplug. The patch introduces one bitmap to PHB to trace the available DMA32 segments for allocation, more fields to "struct pnv_ioda_pe" to trace the consumed DMA32 segments by the PE, which is going to be released when the PE is destroyed at PCI unplugging time. Signed-off-by: Gavin Shan --- v5: * Split from PATCH[v4 07/21] * Added space before open parenthesis reported by checkpatch.pl --- arch/powerpc/platforms/powernv/pci-ioda.c | 24 +++++++++++++++++++++++- arch/powerpc/platforms/powernv/pci.h | 4 ++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 63fad4d..2087c5c 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -2071,6 +2071,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, /* Grab a 32-bit TCE table */ pe->dma32_seg = base; + pe->dma32_segcount = segs; pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", (base << 28), ((base + segs) << 28) - 1); @@ -2131,8 +2132,10 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, return; fail: /* XXX Failure: Try to fallback to 64-bit only ? */ - if (pe->dma32_seg >= 0) + if (pe->dma32_seg >= 0) { + bitmap_clear(phb->ioda.dma32_segmap, base, segs); pe->dma32_seg = -1; + } if (tce_mem) __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); if (tbl) { @@ -2531,6 +2534,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, /* The PE will reserve all possible 32-bits space */ pe->dma32_seg = 0; + pe->dma32_segcount = 1; pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", phb->ioda.m32_pci_base); @@ -2588,6 +2592,24 @@ static void pnv_ioda_setup_dma(struct pnv_phb *phb, struct pnv_ioda_pe *pe) segs = (pe->dma32_weight * phb->ioda.dma32_segcount) / dma_weight; + /* Allocate DMA32 segments as required. We might not have + * enough available resource. However, we expect at least + * one segment is allocated. + */ + do { + base = bitmap_find_next_zero_area( + phb->ioda.dma32_segmap, + phb->ioda.dma32_segcount, + 0, segs, 0); + if (base < phb->ioda.dma32_segcount) { + bitmap_set(phb->ioda.dma32_segmap, base, segs); + break; + } + } while (--segs); + + if (!segs) + return; + pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", pe->dma32_weight, segs); pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h index 5ea33ca..94ef1df 100644 --- a/arch/powerpc/platforms/powernv/pci.h +++ b/arch/powerpc/platforms/powernv/pci.h @@ -61,6 +61,7 @@ struct pnv_ioda_pe { /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ struct iommu_table_group table_group; int dma32_seg; + int dma32_segcount; unsigned int dma32_weight; /* 64-bit TCE bypass region */ @@ -161,6 +162,9 @@ struct pnv_phb { unsigned long m32_segmap[8]; unsigned long m64_segmap[8]; + /* DMA32 segment maps */ + unsigned long dma32_segmap[8]; + /* IRQ chip */ int irq_chip_init; struct irq_chip irq_chip;