From patchwork Thu Jun 4 06:41:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 6544001 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 23D5F9F326 for ; Thu, 4 Jun 2015 06:43:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3B9672075F for ; Thu, 4 Jun 2015 06:43:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3F13D20752 for ; Thu, 4 Jun 2015 06:43:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752524AbbFDGnk (ORCPT ); Thu, 4 Jun 2015 02:43:40 -0400 Received: from e23smtp03.au.ibm.com ([202.81.31.145]:54960 "EHLO e23smtp03.au.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750978AbbFDGnk (ORCPT ); Thu, 4 Jun 2015 02:43:40 -0400 Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jun 2015 16:43:36 +1000 Received: from d23relay09.au.ibm.com (d23relay09.au.ibm.com [9.185.63.181]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 77808357804C; Thu, 4 Jun 2015 16:43:35 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t546hRe611599886; Thu, 4 Jun 2015 16:43:35 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t546h1A3005337; Thu, 4 Jun 2015 16:43:03 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t546h1oL004584; Thu, 4 Jun 2015 16:43:01 +1000 Received: from bran.ozlabs.ibm.com (unknown [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 8566CA03D2; Thu, 4 Jun 2015 16:42:24 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 9075DE387C; Thu, 4 Jun 2015 16:42:24 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id 7FC6A9422B2; Thu, 4 Jun 2015 16:42:24 +1000 (AEST) From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, benh@kernel.crashing.org, bhelgaas@google.com, aik@ozlabs.ru, panto@antoniou-consulting.com, robherring2@gmail.com, grant.likely@linaro.org, Gavin Shan Subject: [PATCH v5 05/42] powerpc/powernv: Simplify pnv_ioda_setup_pe_seg() Date: Thu, 4 Jun 2015 16:41:34 +1000 Message-Id: <1433400131-18429-6-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1433400131-18429-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1433400131-18429-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15060406-0009-0000-0000-00000183D94A Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The original implementation of pnv_ioda_setup_pe_seg() configures IO and M32 segments by separate logics, which can be merged by by caching @seg_bitmap, @seg_size, @win in advance. The patch shouldn't cause any behavioural changes. Signed-off-by: Gavin Shan --- v5: * Split from PATCH[v4 04/21] * Fixed coding style complained by checkpatch.pl --- arch/powerpc/platforms/powernv/pci-ioda.c | 67 +++++++++++++++---------------- 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 53d0efd..3bb4ce8 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -2971,7 +2971,10 @@ static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, struct pci_bus_region region; struct resource *res; int i, index; - int rc; + unsigned int segsize; + unsigned long *segmap, *pe_segmap; + uint16_t win; + int64_t rc; /* * NOTE: We only care PCI bus based PE for now. For PCI @@ -2988,50 +2991,44 @@ static void pnv_ioda_setup_pe_seg(struct pci_controller *hose, if (res->flags & IORESOURCE_IO) { region.start = res->start - phb->ioda.io_pci_base; region.end = res->end - phb->ioda.io_pci_base; - index = region.start / phb->ioda.io_segsize; - - while (index < phb->ioda.total_pe && - region.start <= region.end) { - set_bit(index, phb->ioda.io_segmap); - set_bit(index, pe->io_segmap); - rc = opal_pci_map_pe_mmio_window(phb->opal_id, - pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); - if (rc != OPAL_SUCCESS) { - pr_err("%s: OPAL error %d when mapping IO " - "segment #%d to PE#%d\n", - __func__, rc, index, pe->pe_number); - break; - } - - region.start += phb->ioda.io_segsize; - index++; - } + segsize = phb->ioda.io_segsize; + segmap = phb->ioda.io_segmap; + pe_segmap = pe->io_segmap; + win = OPAL_IO_WINDOW_TYPE; } else if ((res->flags & IORESOURCE_MEM) && - !pnv_pci_is_mem_pref_64(res->flags)) { + !pnv_pci_is_mem_pref_64(res->flags)) { region.start = res->start - hose->mem_offset[0] - phb->ioda.m32_pci_base; region.end = res->end - hose->mem_offset[0] - phb->ioda.m32_pci_base; - index = region.start / phb->ioda.m32_segsize; + segsize = phb->ioda.m32_segsize; + segmap = phb->ioda.m32_segmap; + pe_segmap = pe->m32_segmap; + win = OPAL_M32_WINDOW_TYPE; + } else { + continue; + } - while (index < phb->ioda.total_pe && - region.start <= region.end) { - set_bit(index, phb->ioda.m32_segmap); - set_bit(index, pe->m32_segmap); - rc = opal_pci_map_pe_mmio_window(phb->opal_id, - pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); - if (rc != OPAL_SUCCESS) { - pr_err("%s: OPAL error %d when mapping M32 " - "segment#%d to PE#%d", - __func__, rc, index, pe->pe_number); - break; - } + index = region.start / phb->ioda.io_segsize; + while (index < phb->ioda.total_pe && + region.start <= region.end) { + set_bit(index, segmap); + set_bit(index, pe_segmap); - region.start += phb->ioda.m32_segsize; - index++; + rc = opal_pci_map_pe_mmio_window(phb->opal_id, + pe->pe_number, win, 0, index); + if (rc != OPAL_SUCCESS) { + pr_warn("%s: Error %lld mapping (%d) seg#%d to PHB#%d-PE#%d\n", + __func__, rc, win, index, + pe->phb->hose->global_number, + pe->pe_number); + break; } + + region.start += segsize; + index++; } } }