From patchwork Thu Jun 4 06:41:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 6544181 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 685119F6CE for ; Thu, 4 Jun 2015 06:44:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4532A20752 for ; Thu, 4 Jun 2015 06:44:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1681D2075F for ; Thu, 4 Jun 2015 06:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752584AbbFDGoJ (ORCPT ); Thu, 4 Jun 2015 02:44:09 -0400 Received: from e23smtp07.au.ibm.com ([202.81.31.140]:37246 "EHLO e23smtp07.au.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752590AbbFDGnu (ORCPT ); Thu, 4 Jun 2015 02:43:50 -0400 Received: from /spool/local by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 4 Jun 2015 16:43:45 +1000 Received: from d23relay09.au.ibm.com (d23relay09.au.ibm.com [9.185.63.181]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id 9C17A2BB0054; Thu, 4 Jun 2015 16:43:45 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t546ha0O54526038; Thu, 4 Jun 2015 16:43:45 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t546hBKN006151; Thu, 4 Jun 2015 16:43:12 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t546hBB6004881; Thu, 4 Jun 2015 16:43:11 +1000 Received: from bran.ozlabs.ibm.com (unknown [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id D8C85A03E0; Thu, 4 Jun 2015 16:42:25 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id E2F25E387C; Thu, 4 Jun 2015 16:42:25 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id D20CA9422B2; Thu, 4 Jun 2015 16:42:25 +1000 (AEST) From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, benh@kernel.crashing.org, bhelgaas@google.com, aik@ozlabs.ru, panto@antoniou-consulting.com, robherring2@gmail.com, grant.likely@linaro.org, Gavin Shan Subject: [PATCH v5 08/42] powerpc/powernv: DMA32 cleanup Date: Thu, 4 Jun 2015 16:41:37 +1000 Message-Id: <1433400131-18429-9-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1433400131-18429-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1433400131-18429-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15060406-0025-0000-0000-0000019D2FE4 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch cleans up DMA32 in pci-ioda.c. It shouldn't introduce behavioural changes: * Rename various fields in "struct pnv_phb" and "struct pnv_ioda_pe" as 32-bits DMA should be related to "DMA", not "TCE", and move them around to reflect their relationship and their relative importance. * Removed struct pnv_ioda_pe::tce32_segcount. Signed-off-by: Gavin Shan --- v5: * Split from PATCH[v4 5/21] --- arch/powerpc/platforms/powernv/pci-ioda.c | 48 +++++++++++++++---------------- arch/powerpc/platforms/powernv/pci.h | 13 +++------ 2 files changed, 28 insertions(+), 33 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index d9ff739..4af3d06 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -971,7 +971,7 @@ static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb, struct pnv_ioda_pe *lpe; list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) { - if (lpe->dma_weight < pe->dma_weight) { + if (lpe->dma32_weight < pe->dma32_weight) { list_add_tail(&pe->dma_link, &lpe->dma_link); return; } @@ -996,14 +996,14 @@ static unsigned int pnv_ioda_dev_dma_weight(struct pci_dev *dev) if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || dev->class == PCI_CLASS_SERIAL_USB_OHCI || dev->class == PCI_CLASS_SERIAL_USB_EHCI) - return 3 * phb->ioda.tce32_count; + return 3 * phb->ioda.dma32_segcount; /* Increase the weight of RAID (includes Obsidian) */ if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) - return 15 * phb->ioda.tce32_count; + return 15 * phb->ioda.dma32_segcount; /* Default */ - return 10 * phb->ioda.tce32_count; + return 10 * phb->ioda.dma32_segcount; } static int __pnv_ioda_phb_dma_weight(struct pci_dev *pdev, void *data) @@ -1182,7 +1182,7 @@ static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) continue; } pdn->pe_number = pe->pe_number; - pe->dma_weight += pnv_ioda_dev_dma_weight(dev); + pe->dma32_weight += pnv_ioda_dev_dma_weight(dev); if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) pnv_ioda_setup_same_PE(dev->subordinate, pe); } @@ -1219,10 +1219,10 @@ static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all) pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); pe->pbus = bus; pe->pdev = NULL; - pe->tce32_seg = -1; + pe->dma32_seg = -1; pe->mve_number = -1; pe->rid = bus->busn_res.start << 8; - pe->dma_weight = 0; + pe->dma32_weight = 0; if (all) pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", @@ -1585,7 +1585,7 @@ static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) pe->flags = PNV_IODA_PE_VF; pe->pbus = NULL; pe->parent_dev = pdev; - pe->tce32_seg = -1; + pe->dma32_seg = -1; pe->mve_number = -1; pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | pci_iov_virtfn_devfn(pdev, vf_index); @@ -2061,7 +2061,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, /* XXX FIXME: Allocate multi-level tables on PHB3 */ /* We shouldn't already have a 32-bit DMA associated */ - if (WARN_ON(pe->tce32_seg >= 0)) + if (WARN_ON(pe->dma32_seg >= 0)) return; tbl = pnv_pci_table_alloc(phb->hose->node); @@ -2070,7 +2070,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); /* Grab a 32-bit TCE table */ - pe->tce32_seg = base; + pe->dma32_seg = base; pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", (base << 28), ((base + segs) << 28) - 1); @@ -2131,8 +2131,8 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb, return; fail: /* XXX Failure: Try to fallback to 64-bit only ? */ - if (pe->tce32_seg >= 0) - pe->tce32_seg = -1; + if (pe->dma32_seg >= 0) + pe->dma32_seg = -1; if (tce_mem) __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs)); if (tbl) { @@ -2520,7 +2520,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, int64_t rc; /* We shouldn't already have a 32-bit DMA associated */ - if (WARN_ON(pe->tce32_seg >= 0)) + if (WARN_ON(pe->dma32_seg >= 0)) return; /* TVE #1 is selected by PCI address bit 59 */ @@ -2530,7 +2530,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, pe->pe_number); /* The PE will reserve all possible 32-bits space */ - pe->tce32_seg = 0; + pe->dma32_seg = 0; pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", phb->ioda.m32_pci_base); @@ -2547,8 +2547,8 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, rc = pnv_pci_ioda2_setup_default_config(pe); if (rc) { - if (pe->tce32_seg >= 0) - pe->tce32_seg = -1; + if (pe->dma32_seg >= 0) + pe->dma32_seg = -1; return; } @@ -2567,7 +2567,7 @@ static void pnv_ioda_setup_dma(struct pnv_phb *phb) /* Calculate the PHB's DMA weight */ dma_weight = pnv_ioda_phb_dma_weight(phb); pr_info("PCI%04x has %ld DMA32 segments, total weight %d\n", - hose->global_number, phb->ioda.tce32_count, dma_weight); + hose->global_number, phb->ioda.dma32_segcount, dma_weight); pnv_pci_ioda_setup_opal_tce_kill(phb); @@ -2576,7 +2576,7 @@ static void pnv_ioda_setup_dma(struct pnv_phb *phb) * weight */ list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { - if (!pe->dma_weight) + if (!pe->dma32_weight) continue; /* @@ -2587,15 +2587,15 @@ static void pnv_ioda_setup_dma(struct pnv_phb *phb) if (phb->type == PNV_PHB_IODA1) { unsigned int segs, base = 0; - if (pe->dma_weight < - dma_weight / phb->ioda.tce32_count) + if (pe->dma32_weight < + dma_weight / phb->ioda.dma32_segcount) segs = 1; else - segs = (pe->dma_weight * - phb->ioda.tce32_count) / dma_weight; + segs = (pe->dma32_weight * + phb->ioda.dma32_segcount) / dma_weight; pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", - pe->dma_weight, segs); + pe->dma32_weight, segs); pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs); base += segs; @@ -3314,7 +3314,7 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np, mutex_init(&phb->ioda.pe_list_mutex); /* Calculate how many 32-bit TCE segments we have */ - phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28; + phb->ioda.dma32_segcount = phb->ioda.m32_pci_base >> 28; #if 0 /* We should really do that ... */ rc = opal_pci_set_phb_mem_window(opal->phb_id, diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h index 38d8616..5ea33ca 100644 --- a/arch/powerpc/platforms/powernv/pci.h +++ b/arch/powerpc/platforms/powernv/pci.h @@ -58,15 +58,10 @@ struct pnv_ioda_pe { unsigned long m32_segmap[8]; unsigned long m64_segmap[8]; - /* "Weight" assigned to the PE for the sake of DMA resource - * allocations - */ - unsigned int dma_weight; - /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */ - int tce32_seg; - int tce32_segcount; struct iommu_table_group table_group; + int dma32_seg; + unsigned int dma32_weight; /* 64-bit TCE bypass region */ bool tce_bypass_enabled; @@ -182,8 +177,8 @@ struct pnv_phb { */ unsigned char pe_rmap[0x10000]; - /* 32-bit TCE tables allocation */ - unsigned long tce32_count; + /* Number of 32-bit DMA segments */ + unsigned long dma32_segcount; /* Sorted list of used PE's, sorted at * boot for resource allocation purposes