From patchwork Wed Jul 29 22:18:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Keith Busch X-Patchwork-Id: 6896421 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 88D92C05AC for ; Wed, 29 Jul 2015 22:20:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A6884205F0 for ; Wed, 29 Jul 2015 22:20:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 73B4C205F9 for ; Wed, 29 Jul 2015 22:20:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753825AbbG2WTg (ORCPT ); Wed, 29 Jul 2015 18:19:36 -0400 Received: from mga11.intel.com ([192.55.52.93]:47339 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752025AbbG2WTe (ORCPT ); Wed, 29 Jul 2015 18:19:34 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP; 29 Jul 2015 15:19:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,572,1432623600"; d="scan'208";a="615509316" Received: from dcgshare.lm.intel.com ([10.232.118.254]) by orsmga003.jf.intel.com with ESMTP; 29 Jul 2015 15:19:33 -0700 Received: by dcgshare.lm.intel.com (Postfix, from userid 1017) id B4B47E00EA; Wed, 29 Jul 2015 16:19:32 -0600 (MDT) From: Keith Busch To: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Bjorn Helgass , Dave Jiang Subject: [PATCH 2/3] QIB: Removing usage of pcie_set_mps() Date: Wed, 29 Jul 2015 16:18:54 -0600 Message-Id: <1438208335-19457-3-git-send-email-keith.busch@intel.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1438208335-19457-1-git-send-email-keith.busch@intel.com> References: <1438208335-19457-1-git-send-email-keith.busch@intel.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dave Jiang This is in perperation of un-exporting the pcie_set_mps() function symbol. A driver should not be changing the MPS as that is the responsibility of the PCI subsystem. Signed-off-by: Dave Jiang --- drivers/infiniband/hw/qib/qib_pcie.c | 27 +-------------------------- 1 file changed, 1 insertion(+), 26 deletions(-) diff --git a/drivers/infiniband/hw/qib/qib_pcie.c b/drivers/infiniband/hw/qib/qib_pcie.c index 4758a38..b8a2dcd 100644 --- a/drivers/infiniband/hw/qib/qib_pcie.c +++ b/drivers/infiniband/hw/qib/qib_pcie.c @@ -557,12 +557,11 @@ static void qib_tune_pcie_coalesce(struct qib_devdata *dd) */ static int qib_pcie_caps; module_param_named(pcie_caps, qib_pcie_caps, int, S_IRUGO); -MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)"); +MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: ReadReq (4..7)"); static void qib_tune_pcie_caps(struct qib_devdata *dd) { struct pci_dev *parent; - u16 rc_mpss, rc_mps, ep_mpss, ep_mps; u16 rc_mrrs, ep_mrrs, max_mrrs; /* Find out supported and configured values for parent (root) */ @@ -575,30 +574,6 @@ static void qib_tune_pcie_caps(struct qib_devdata *dd) if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) return; - rc_mpss = parent->pcie_mpss; - rc_mps = ffs(pcie_get_mps(parent)) - 8; - /* Find out supported and configured values for endpoint (us) */ - ep_mpss = dd->pcidev->pcie_mpss; - ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; - - /* Find max payload supported by root, endpoint */ - if (rc_mpss > ep_mpss) - rc_mpss = ep_mpss; - - /* If Supported greater than limit in module param, limit it */ - if (rc_mpss > (qib_pcie_caps & 7)) - rc_mpss = qib_pcie_caps & 7; - /* If less than (allowed, supported), bump root payload */ - if (rc_mpss > rc_mps) { - rc_mps = rc_mpss; - pcie_set_mps(parent, 128 << rc_mps); - } - /* If less than (allowed, supported), bump endpoint payload */ - if (rc_mpss > ep_mps) { - ep_mps = rc_mpss; - pcie_set_mps(dd->pcidev, 128 << ep_mps); - } - /* * Now the Read Request size. * No field for max supported, but PCIe spec limits it to 4096,