From patchwork Fri Jul 31 02:15:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 6907941 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 634889F358 for ; Fri, 31 Jul 2015 02:15:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4E3E0205EA for ; Fri, 31 Jul 2015 02:15:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 09DDD20602 for ; Fri, 31 Jul 2015 02:15:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752422AbbGaCPP (ORCPT ); Thu, 30 Jul 2015 22:15:15 -0400 Received: from bh-25.webhostbox.net ([208.91.199.152]:33960 "EHLO bh-25.webhostbox.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752107AbbGaCPN (ORCPT ); Thu, 30 Jul 2015 22:15:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=roeck-us.net; s=default; h=Message-Id:Date:Subject:Cc:To:From; bh=9nq2m7ytHG/0d5dLAyNIRg23Nq2Ekgo/kwaMIRWeE5Q=; b=WKn+BrA0SmdrUJ6ZurraXL25ltb6jJWBOQqUD3wpSrzGkeKwEU4+0/NTb8s7qXHUuhywJpAe3HL3i5hpX9k5DKKqftetjjBwz8nWhMRdZqmd0NhIW1v1PZzHpbkyudKVrB6OSDUsm3TFacr4QmpBQqq0FUNcOiK2DQxtCrJ30cg=; Received: from 108-223-40-66.lightspeed.sntcca.sbcglobal.net ([108.223.40.66]:47917 helo=localhost) by bh-25.webhostbox.net with esmtpa (Exim 4.85) (envelope-from ) id 1ZKzqo-0036rK-1z; Fri, 31 Jul 2015 02:15:11 +0000 From: Guenter Roeck To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Guenter Roeck , Lorenzo Pieralisi , Yinghai Lu Subject: [PATCH v3] PCI: Only enable IO window if supported Date: Thu, 30 Jul 2015 19:15:08 -0700 Message-Id: <1438308908-12259-1-git-send-email-linux@roeck-us.net> X-Mailer: git-send-email 2.1.4 X-Authenticated_sender: guenter@roeck-us.net X-OutGoing-Spam-Status: No, score=-1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - bh-25.webhostbox.net X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - roeck-us.net X-Get-Message-Sender-Via: bh-25.webhostbox.net: authenticated_id: guenter@roeck-us.net X-Source: X-Source-Args: X-Source-Dir: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PCI subsystem always assumes that I/O is supported on PCIe bridges and tries to assign an I/O window to each child bus even if that is not the case. This may result in messages such as: pcieport 0000:02:00.0: res[7]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 pcieport 0000:02:00.0: BAR 7: no space for [io size 0x1000] pcieport 0000:02:00.0: BAR 7: failed to assign [io size 0x1000] for each bridge port, even if a bus or its parent does not support I/O in the first place. To avoid this message, check if a bus supports I/O before trying to enable it. Also check if the root bus has an IO window assigned; if not, it does not make sense to try to assign one to any of its child busses. Cc: Lorenzo Pieralisi Cc: Yinghai Lu Signed-off-by: Guenter Roeck --- v3: Reverse order of new flag, and name it PCI_BUS_FLAGS_SUPPORTS_IO instead of PCI_BUS_FLAGS_NO_IO. Don't use bool in pci_bridge_supports_io. Drop pci_root_has_io_resource(). Instead, determine if the root bus has an io window in pci_create_root_bus(), and clear PCI_BUS_FLAGS_SUPPORTS_IO in its bus flags if it doesn't. v2: Use a new bus flag to indicate if IO is supported on a bus or not. Using IORESOURCE_DISABLED in resource flags turned out to be futile, since the term "!res->flags" is widely used to detect if a resource window is enabled or not, and setting IORESOURCE_DISABLED would affect all this code. This patch depends on 'PCI: move pci_read_bridge_bases to the generic PCI layer' by Lorenzo Pieralisi; without it, pci_read_bridge_io() is not always called. --- drivers/pci/probe.c | 34 ++++++++++++++++++++++++++++++++++ drivers/pci/setup-bus.c | 9 +-------- include/linux/pci.h | 1 + 3 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index cefd636681b6..d9e02ba34035 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -332,6 +332,24 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) } } +static int pci_bridge_supports_io(struct pci_dev *bridge) +{ + u16 io; + + pci_read_config_word(bridge, PCI_IO_BASE, &io); + if (io) + return 1; + + /* IO_BASE/LIMIT is either hard-wired to zero or programmed to zero */ + pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); + pci_read_config_word(bridge, PCI_IO_BASE, &io); + pci_write_config_word(bridge, PCI_IO_BASE, 0x0); + if (io) + return 1; + + return 0; +} + static void pci_read_bridge_io(struct pci_bus *child) { struct pci_dev *dev = child->self; @@ -340,6 +358,15 @@ static void pci_read_bridge_io(struct pci_bus *child) struct pci_bus_region region; struct resource *res; + if (!(child->bus_flags & PCI_BUS_FLAGS_SUPPORTS_IO)) + return; + + if (!pci_bridge_supports_io(dev)) { + dev_printk(KERN_DEBUG, &dev->dev, " no I/O window\n"); + child->bus_flags &= ~PCI_BUS_FLAGS_SUPPORTS_IO; + return; + } + io_mask = PCI_IO_RANGE_MASK; io_granularity = 0x1000; if (dev->io_window_1k) { @@ -496,6 +523,7 @@ static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) INIT_LIST_HEAD(&b->resources); b->max_bus_speed = PCI_SPEED_UNKNOWN; b->cur_bus_speed = PCI_SPEED_UNKNOWN; + b->bus_flags = PCI_BUS_FLAGS_SUPPORTS_IO; #ifdef CONFIG_PCI_DOMAINS_GENERIC if (parent) b->domain_nr = parent->domain_nr; @@ -1938,6 +1966,7 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, resource_size_t offset; char bus_addr[64]; char *fmt; + bool has_io = false; b = pci_alloc_bus(NULL); if (!b) @@ -2016,8 +2045,13 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, } else bus_addr[0] = '\0'; dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr); + if (resource_type(res) == IORESOURCE_IO) + has_io = true; } + if (!has_io) + b->bus_flags &= ~PCI_BUS_FLAGS_SUPPORTS_IO; + down_write(&pci_bus_sem); list_add_tail(&b->node, &pci_root_buses); up_write(&pci_bus_sem); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 508cc56130e3..c3fdace30faf 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -744,7 +744,6 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, int i) base/limit registers must be read-only and read as 0. */ static void pci_bridge_check_ranges(struct pci_bus *bus) { - u16 io; u32 pmem; struct pci_dev *bridge = bus->self; struct resource *b_res; @@ -752,13 +751,7 @@ static void pci_bridge_check_ranges(struct pci_bus *bus) b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; b_res[1].flags |= IORESOURCE_MEM; - pci_read_config_word(bridge, PCI_IO_BASE, &io); - if (!io) { - pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); - pci_read_config_word(bridge, PCI_IO_BASE, &io); - pci_write_config_word(bridge, PCI_IO_BASE, 0x0); - } - if (io) + if (bus->bus_flags & PCI_BUS_FLAGS_SUPPORTS_IO) b_res[0].flags |= IORESOURCE_IO; /* DECchip 21050 pass 2 errata: the bridge may miss an address diff --git a/include/linux/pci.h b/include/linux/pci.h index 8a0321a8fb59..3bbabf344bfc 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -191,6 +191,7 @@ typedef unsigned short __bitwise pci_bus_flags_t; enum pci_bus_flags { PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, + PCI_BUS_FLAGS_SUPPORTS_IO = (__force pci_bus_flags_t) 4, }; /* These values come from the PCI Express Spec */