From patchwork Mon Oct 12 15:46:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 7377321 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 81AF9BEEA4 for ; Mon, 12 Oct 2015 15:49:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5E8142073E for ; Mon, 12 Oct 2015 15:49:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 259AE20522 for ; Mon, 12 Oct 2015 15:49:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751613AbbJLPtV (ORCPT ); Mon, 12 Oct 2015 11:49:21 -0400 Received: from mail-qk0-f170.google.com ([209.85.220.170]:33196 "EHLO mail-qk0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751094AbbJLPtU (ORCPT ); Mon, 12 Oct 2015 11:49:20 -0400 Received: by qkas79 with SMTP id s79so59513636qka.0 for ; Mon, 12 Oct 2015 08:49:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=O+/f6crkZDLjSfbHuhLG5Ep6hjtxLYACa7whQ5VKIdc=; b=t+iLT/+CAMp3TDpdEc+/AFuCjNQAAckXpTKMsl8/7p7R6gkd0Ygb/Cw60naEF+hTGz KBdPUAS1DCvMXdY945+m+Kaab1txZYMDWb41GCLbRJhum12QPz0kaPiWjKisi8xK+fsj cgmIFYMXKkhhkG9aSLMNe7yI60SF4ko3dY1l770b/DLU58cUWsdqkzLoV7kwZIiuFI7B NAam7OjTaqwInCdI4ykF0kTv6ug8pIlox+jTinnP0tuW2rPI7bQc4KdnZHzJp4xrlHdR lMQmxTb8Zo0bHtMEuuzhoOKetfX4K+Wy6oci68DgUzJ6GVyoc/zRGOMmiBs0+4zWupW6 wyHw== X-Received: by 10.55.200.71 with SMTP id c68mr28757543qkj.72.1444664959768; Mon, 12 Oct 2015 08:49:19 -0700 (PDT) Received: from localhost.localdomain ([189.5.18.107]) by smtp.gmail.com with ESMTPSA id 5sm7361990qkq.19.2015.10.12.08.48.49 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Oct 2015 08:48:51 -0700 (PDT) From: Fabio Estevam To: bhelgaas@google.com Cc: pratyush.anand@gmail.com, m-karicheri2@ti.com, l.stach@pengutronix.de, linux-pci@vger.kernel.org, Fabio Estevam Subject: [PATCH v3 1/3] PCI: designware: Move LTSSM state definitions to pcie-designware.h Date: Mon, 12 Oct 2015 12:46:46 -0300 Message-Id: <1444664808-16445-1-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Fabio Estevam Move LTSSM state definitions to common pcie-designware.h so that other drivers can make use of them. Also, LTSSM states only use 5 bits so use 0x1f as its mask, so that we have a common LTSSM mask accross all PCIe designware drivers. Keystone uses 5 bits for the LTSSM in its reference manual, others like i.MX6 uses 6 bits. However, the LTSSM states really have 5 bits, so we can safely use 5 bits (which corresponds to the 0x1f mask) for all the PCIe Designware cores. Signed-off-by: Fabio Estevam Reviewed-by: Lucas Stach --- Changes since v2: - Use LTSSM_STATE_MASK with value 0x1f for all the drivers (Lucas) - Use lowercase in pcie-designware.h (Lucas) drivers/pci/host/pci-keystone-dw.c | 1 - drivers/pci/host/pci-layerscape.c | 1 - drivers/pci/host/pcie-designware.h | 34 ++++++++++++++++++++++++++++++++++ drivers/pci/host/pcie-spear13xx.c | 33 --------------------------------- 4 files changed, 34 insertions(+), 35 deletions(-) diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c index 0146b41..76edf92 100644 --- a/drivers/pci/host/pci-keystone-dw.c +++ b/drivers/pci/host/pci-keystone-dw.c @@ -25,7 +25,6 @@ /* Application register defines */ #define LTSSM_EN_VAL 1 -#define LTSSM_STATE_MASK 0x1f #define LTSSM_STATE_L0 0x11 #define DBI_CS2_EN_VAL 0x20 #define OB_XLAT_EN_VAL 2 diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 495a7c3..f68b551 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -28,7 +28,6 @@ /* PEX1/2 Misc Ports Status Register */ #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) #define LTSSM_STATE_SHIFT 20 -#define LTSSM_STATE_MASK 0x3f #define LTSSM_PCIE_L0 0x11 /* L0 state */ /* PEX Internal Configuration Registers */ diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index e7b3279..95846dd 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -22,6 +22,40 @@ #define MAX_MSI_IRQS 32 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) +#define LTSSM_STATE_DETECT_QUIET 0x00 +#define LTSSM_STATE_DETECT_ACT 0x01 +#define LTSSM_STATE_POLL_ACTIVE 0x02 +#define LTSSM_STATE_POLL_COMPLIANCE 0x03 +#define LTSSM_STATE_POLL_CONFIG 0x04 +#define LTSSM_STATE_PRE_DETECT_QUIET 0x05 +#define LTSSM_STATE_DETECT_WAIT 0x06 +#define LTSSM_STATE_CFG_LINKWD_START 0x07 +#define LTSSM_STATE_CFG_LINKWD_ACEPT 0x08 +#define LTSSM_STATE_CFG_LANENUM_WAIT 0x09 +#define LTSSM_STATE_CFG_LANENUM_ACEPT 0x0a +#define LTSSM_STATE_CFG_COMPLETE 0x0b +#define LTSSM_STATE_CFG_IDLE 0x0c +#define LTSSM_STATE_RCVRY_LOCK 0x0d +#define LTSSM_STATE_RCVRY_SPEED 0x0e +#define LTSSM_STATE_RCVRY_RCVRCFG 0x0f +#define LTSSM_STATE_RCVRY_IDLE 0x10 +#define LTSSM_STATE_L0 0x11 +#define LTSSM_STATE_L0S 0x12 +#define LTSSM_STATE_L123_SEND_EIDLE 0x13 +#define LTSSM_STATE_L1_IDLE 0x14 +#define LTSSM_STATE_L2_IDLE 0x15 +#define LTSSM_STATE_L2_WAKE 0x16 +#define LTSSM_STATE_DISABLED_ENTRY 0x17 +#define LTSSM_STATE_DISABLED_IDLE 0x18 +#define LTSSM_STATE_DISABLED 0x19 +#define LTSSM_STATE_LPBK_ENTRY 0x1a +#define LTSSM_STATE_LPBK_ACTIVE 0x1b +#define LTSSM_STATE_LPBK_EXIT 0x1c +#define LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1d +#define LTSSM_STATE_HOT_RESET_ENTRY 0x1e +#define LTSSM_STATE_HOT_RESET 0x1f +#define LTSSM_STATE_MASK 0x1f + struct pcie_port { struct device *dev; u8 root_bus_nr; diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c index b95b756..8f0a1a2 100644 --- a/drivers/pci/host/pcie-spear13xx.c +++ b/drivers/pci/host/pcie-spear13xx.c @@ -84,39 +84,6 @@ struct pcie_app_reg { #define APPS_PM_XMT_PME_ID 5 /* CR3 ID */ -#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00 -#define XMLH_LTSSM_STATE_DETECT_ACT 0x01 -#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02 -#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03 -#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04 -#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05 -#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06 -#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07 -#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08 -#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09 -#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A -#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B -#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C -#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D -#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E -#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F -#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10 -#define XMLH_LTSSM_STATE_L0 0x11 -#define XMLH_LTSSM_STATE_L0S 0x12 -#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13 -#define XMLH_LTSSM_STATE_L1_IDLE 0x14 -#define XMLH_LTSSM_STATE_L2_IDLE 0x15 -#define XMLH_LTSSM_STATE_L2_WAKE 0x16 -#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17 -#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18 -#define XMLH_LTSSM_STATE_DISABLED 0x19 -#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A -#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B -#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C -#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D -#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E -#define XMLH_LTSSM_STATE_HOT_RESET 0x1F -#define XMLH_LTSSM_STATE_MASK 0x3F #define XMLH_LINK_UP (1 << 6) /* CR4 ID */