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BY1PR0301MB1256; 5:q3fLkzcrDFIErcG6Bi/h01mYB4rcQ6mQr/CaIIOlfTHQ3PrTr3DKIWnv2LSNnkogrTQyTqRWHZY81Z/ErOKc1LxFls5HIRBbWq+hL8BRnxmlJQMzIdivUe9iXaJIpJRXlFvAs8ZJrCwdpj5vsihlEQ==; 24:CXsqDc0Qa/fPDxZHSiRLzHMfFmVkKgO8YYfCptgYWVc7LY7EvCgrquUvzCQ2cfmKIpRpJbr6j7g6XZ7BTNkgcXvIYDbIMWPBFPkHhDMa/48=; 20:ybiGKNU5TXr5Rj39zEQI8+8foPLGM3SFYn2UuNh/bA8JQrOKtgdtHANQvEtJj66r5Wgi/Hb5ThVvedL/E/t4oQ== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2015 07:18:38.8678 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0301MB1256 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Layerscape PCIe controller supports root complex (RC) and endpoint (EP) mode. The mode can be set by RCW. The patch will check it. If not in RC mode, the driver directly returns -ENODEV. Signed-off-by: Minghuan Lian --- Change log v4: split from [PATCH v3] PCI: layerscape: Add PCIe support for LS1043a and LS2080a drivers/pci/host/pci-layerscape.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 6dd44a0..5eabe92 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -47,6 +47,16 @@ struct ls_pcie { #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) +static bool ls_pcie_is_bridge(struct ls_pcie *pcie) +{ + u32 header_type; + + header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE); + header_type &= 0x7f; + + return header_type == PCI_HEADER_TYPE_BRIDGE; +} + static int ls_pcie_link_up(struct pcie_port *pp) { u32 state; @@ -135,6 +145,9 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return ret; pcie->index = index[1]; + if (!ls_pcie_is_bridge(pcie)) + return -ENODEV; + ret = ls_add_pcie_port(pcie); if (ret < 0) return ret;