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BY2PR03MB571; 5:0JzgFdaJ9V67MfzYw8WnI/Ow1QDa6nRHuEKEOc2j1k4r6XLNC6Y59crT3KZ1OiCapdiIR9ne79V3MH6nBTLVXjF0pQZhVnJ5TpMqtfarbkXrxUh/ecSOIeboETc6sWXcUcHSo5wMVDQpdzZz2d8nxw==; 24:qhPMvEtMN2VdnVJWGvdb0JMYZchefQzfqBsa6KFDL7NZDcLYnQJC5/O0+riN5m9+BOBEV5vUJRteL1INLMklrSN7hwd23gyiHkyVJOO5XTU=; 20:WzsM5535HkyaPmFXVoyBMFl0gGz0aK2oztyE8JWFc8nySkY4qvdUxaqaAQHcphz6ATGKP5VxW3quyBrqzrd66w== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2015 07:18:42.1082 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR03MB571 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For LS1021a PCIe controller, some status registers are located in SCFG. This is different to other kind of Layerscape. The patch moves SCFG related code to ls1021_pcie_host_init() and rename ls_pcie_link_up to ls1021_pcie_link_up because LTSSM status is also in SCFG. Signed-off-by: Minghuan Lian --- Change log v4: split from [PATCH v3] PCI: layerscape: Add PCIe support for LS1043a and LS2080a drivers/pci/host/pci-layerscape.c | 72 +++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 26 deletions(-) diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 5eabe92..89b7eb8 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -34,6 +34,10 @@ /* Symbol Timer Register and Filter Mask Register 1 */ #define PCIE_STRFMR1 0x71c +struct ls_pcie_drvdata { + struct pcie_host_ops *ops; +}; + struct ls_pcie { struct list_head node; struct device *dev; @@ -41,6 +45,7 @@ struct ls_pcie { void __iomem *dbi; struct regmap *scfg; struct pcie_port pp; + const struct ls_pcie_drvdata *drvdata; int index; int msi_irq; }; @@ -57,11 +62,14 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie) return header_type == PCI_HEADER_TYPE_BRIDGE; } -static int ls_pcie_link_up(struct pcie_port *pp) +static int ls1021_pcie_link_up(struct pcie_port *pp) { u32 state; struct ls_pcie *pcie = to_ls_pcie(pp); + if (!pcie->scfg) + return 0; + regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; @@ -71,10 +79,25 @@ static int ls_pcie_link_up(struct pcie_port *pp) return 1; } -static void ls_pcie_host_init(struct pcie_port *pp) +static void ls1021_pcie_host_init(struct pcie_port *pp) { struct ls_pcie *pcie = to_ls_pcie(pp); - u32 val; + u32 val, index[2]; + + pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node, + "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(pp->dev, "No syscfg phandle specified\n"); + pcie->scfg = NULL; + return; + } + + if (of_property_read_u32_array(pp->dev->of_node, + "fsl,pcie-scfg", index, 2)) { + pcie->scfg = NULL; + return; + } + pcie->index = index[1]; dw_pcie_setup_rc(pp); @@ -87,11 +110,21 @@ static void ls_pcie_host_init(struct pcie_port *pp) iowrite32(val, pcie->dbi + PCIE_STRFMR1); } -static struct pcie_host_ops ls_pcie_host_ops = { - .link_up = ls_pcie_link_up, - .host_init = ls_pcie_host_init, +static struct pcie_host_ops ls1021_pcie_host_ops = { + .link_up = ls1021_pcie_link_up, + .host_init = ls1021_pcie_host_init, +}; + +static struct ls_pcie_drvdata ls1021_drvdata = { + .ops = &ls1021_pcie_host_ops, }; +static const struct of_device_id ls_pcie_of_match[] = { + { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, + { }, +}; +MODULE_DEVICE_TABLE(of, ls_pcie_of_match); + static int ls_add_pcie_port(struct ls_pcie *pcie) { struct pcie_port *pp; @@ -101,7 +134,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) pp->dev = pcie->dev; pp->dbi_base = pcie->dbi; pp->root_bus_nr = -1; - pp->ops = &ls_pcie_host_ops; + pp->ops = pcie->drvdata->ops; ret = dw_pcie_host_init(pp); if (ret) { @@ -114,11 +147,15 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) static int __init ls_pcie_probe(struct platform_device *pdev) { + const struct of_device_id *match; struct ls_pcie *pcie; struct resource *dbi_base; - u32 index[2]; int ret; + match = of_match_device(ls_pcie_of_match, &pdev->dev); + if (!match) + return -ENODEV; + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; @@ -132,18 +169,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return PTR_ERR(pcie->dbi); } - pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "fsl,pcie-scfg"); - if (IS_ERR(pcie->scfg)) { - dev_err(&pdev->dev, "No syscfg phandle specified\n"); - return PTR_ERR(pcie->scfg); - } - - ret = of_property_read_u32_array(pdev->dev.of_node, - "fsl,pcie-scfg", index, 2); - if (ret) - return ret; - pcie->index = index[1]; + pcie->drvdata = match->data; if (!ls_pcie_is_bridge(pcie)) return -ENODEV; @@ -157,12 +183,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id ls_pcie_of_match[] = { - { .compatible = "fsl,ls1021a-pcie" }, - { }, -}; -MODULE_DEVICE_TABLE(of, ls_pcie_of_match); - static struct platform_driver ls_pcie_driver = { .driver = { .name = "layerscape-pcie",