From patchwork Mon Oct 26 11:02:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 7487101 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3A7799F36A for ; Mon, 26 Oct 2015 11:07:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 90EC1207D4 for ; Mon, 26 Oct 2015 11:07:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9ED3720653 for ; Mon, 26 Oct 2015 11:07:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753616AbbJZLGd (ORCPT ); Mon, 26 Oct 2015 07:06:33 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:14434 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753617AbbJZLG2 (ORCPT ); Mon, 26 Oct 2015 07:06:28 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id t9QB4xNq004531; Mon, 26 Oct 2015 04:05:58 -0700 Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 1xsjg6g2be-1 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 26 Oct 2015 04:05:58 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Mon, 26 Oct 2015 04:05:56 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1044.25 via Frontend Transport; Mon, 26 Oct 2015 04:05:56 -0700 Received: from xhacker.marvell.com (unknown [10.37.135.134]) by maili.marvell.com (Postfix) with ESMTP id C32723F7043; Mon, 26 Oct 2015 04:05:54 -0700 (PDT) From: Jisheng Zhang To: , , , , , , , CC: , , , , , Jisheng Zhang Subject: [RFC PATCH 2/3] PCI: tegra: generate proper configuration access cycles Date: Mon, 26 Oct 2015 19:02:13 +0800 Message-ID: <1445857334-6936-3-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1445857334-6936-1-git-send-email-jszhang@marvell.com> References: <1445857334-6936-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2015-10-26_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510260190 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Inspired by Russell King's patch[1], I found current tegra also has the same issue of "reading 32-bits from the command register, modifying the command register, and then writing it back has the effect of clearing any status bits that were indicating at that time" as pointed out by Russell. This patch fix this issue by using the pci_generic_config_write. [1]http://www.spinics.net/lists/linux-pci/msg44869.html Signed-off-by: Jisheng Zhang --- drivers/pci/host/pci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 81df0c1..d926e3e 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -483,7 +483,7 @@ static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus, static struct pci_ops tegra_pcie_ops = { .map_bus = tegra_pcie_conf_address, .read = pci_generic_config_read32, - .write = pci_generic_config_write32, + .write = pci_generic_config_write, }; static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)