From patchwork Mon Oct 26 21:25:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sinan Kaya X-Patchwork-Id: 7491991 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8EFBDBEEA4 for ; Mon, 26 Oct 2015 21:26:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8DB23206F8 for ; Mon, 26 Oct 2015 21:26:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 96BB7206AF for ; Mon, 26 Oct 2015 21:26:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752895AbbJZVZ7 (ORCPT ); Mon, 26 Oct 2015 17:25:59 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58472 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752790AbbJZVZo (ORCPT ); Mon, 26 Oct 2015 17:25:44 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 13BAC1405B6; Mon, 26 Oct 2015 21:25:44 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 014281405B0; Mon, 26 Oct 2015 21:25:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from drakthul.qualcomm.com (rrcs-67-52-130-30.west.biz.rr.com [67.52.130.30]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: okaya@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id CDCB61405A9; Mon, 26 Oct 2015 21:25:42 +0000 (UTC) From: Sinan Kaya To: linux-pci@vger.kernel.org, timur@codeaurora.org, cov@codeaurora.org, jcm@redhat.com Cc: Sinan Kaya , Bjorn Helgaas , Yijing Wang , linux-kernel@vger.kernel.org Subject: [PATCH] PCI/AER: enable SERR# forwarding and role-based error reporting Date: Mon, 26 Oct 2015 17:25:02 -0400 Message-Id: <1445894704-28277-1-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A PCIe card behind a PCIe switch is unable to report its errors when SERR# forwarding is not enabled on the PCIe switch's secondary interface. This is required by the PCIe spec. This patch enables SERR# forwarding and also cleans out compatibility mode so that AER reporting is enabled. Tested with PEX8749-CA RDK. Signed-off-by: Sinan Kaya --- drivers/pci/pcie/aer/aerdrv_core.c | 56 +++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index 9803e3d..acd22d7 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c @@ -37,21 +37,75 @@ module_param(nosourceid, bool, 0); int pci_enable_pcie_error_reporting(struct pci_dev *dev) { + u8 header_type; + int pos; + if (pcie_aer_get_firmware_first(dev)) return -EIO; - if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)) + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + if (!pos) return -EIO; + pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); + + /* needs to be a bridge/switch */ + if (header_type == PCI_HEADER_TYPE_BRIDGE) { + u32 status; + u16 control; + + /* + * A switch will not forward ERR_ messages coming from an + * endpoint if SERR# forwarding is not enabled. + * AER driver is checking the errors at the root only. + */ + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); + control |= PCI_BRIDGE_CTL_SERR; + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); + + /* + * Need to inform hardware that we support + * Role-Based Error Reporting. + */ + pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &status); + status &= ~PCI_ERR_COR_ADV_NFAT; + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, status); + } + return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS); } EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); int pci_disable_pcie_error_reporting(struct pci_dev *dev) { + int pos; + u8 header_type; + if (pcie_aer_get_firmware_first(dev)) return -EIO; + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + if (!pos) + return -EIO; + + pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); + + /* needs to be a bridge/switch */ + if (header_type == PCI_HEADER_TYPE_BRIDGE) { + u32 status; + u16 control; + + /* clear serr forwarding */ + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); + control &= ~PCI_BRIDGE_CTL_SERR; + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); + + /* set compatibility mode */ + pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &status); + status |= PCI_ERR_COR_ADV_NFAT; + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, status); + } + return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS); }