From patchwork Wed Nov 4 13:12:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 7550361 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A33A19F327 for ; Wed, 4 Nov 2015 13:56:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CBFCD20592 for ; Wed, 4 Nov 2015 13:56:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 73D9920591 for ; Wed, 4 Nov 2015 13:55:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030309AbbKDNz5 (ORCPT ); Wed, 4 Nov 2015 08:55:57 -0500 Received: from e28smtp09.in.ibm.com ([122.248.162.9]:33851 "EHLO e28smtp09.in.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030282AbbKDNzn (ORCPT ); Wed, 4 Nov 2015 08:55:43 -0500 Received: from /spool/local by e28smtp09.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 4 Nov 2015 19:25:39 +0530 X-Helo: d28dlp03.in.ibm.com X-MailFrom: gwshan@linux.vnet.ibm.com X-RcptTo: linux-pci@vger.kernel.org Received: from d28relay03.in.ibm.com (d28relay03.in.ibm.com [9.184.220.60]) by d28dlp03.in.ibm.com (Postfix) with ESMTP id 91971125805D; Wed, 4 Nov 2015 19:25:37 +0530 (IST) Received: from d28av02.in.ibm.com (d28av02.in.ibm.com [9.184.220.64]) by d28relay03.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id tA4DRmdm57933900; Wed, 4 Nov 2015 19:25:37 +0530 Received: from d28av02.in.ibm.com (localhost [127.0.0.1]) by d28av02.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id tA4DDDqF031561; Wed, 4 Nov 2015 18:43:15 +0530 Received: from gwshan ([9.192.177.12]) by d28av02.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with SMTP id tA4DD5FE030910; Wed, 4 Nov 2015 18:43:10 +0530 Received: by gwshan (Postfix, from userid 1000) id 9A125942C4B; Thu, 5 Nov 2015 00:12:59 +1100 (AEDT) From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, benh@kernel.crashing.org, mpe@ellerman.id.au, aik@ozlabs.ru, bhelgaas@google.com, grant.likely@linaro.org, robherring2@gmail.com, panto@antoniou-consulting.com, frowand.list@gmail.com, Gavin Shan Subject: [PATCH v7 17/50] powerpc/powernv: Avoid calculating DMA32 segments on PHB3 Date: Thu, 5 Nov 2015 00:12:17 +1100 Message-Id: <1446642770-4681-18-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1446642770-4681-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1446642770-4681-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15110413-0033-0000-0000-000008B45383 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In pnv_ioda_setup_dma(), it's unnecessary to calculate the DMA32 segments for PEs on PHB3 as the whole available DMA32 space can be assigned to one specific PE on PHB3. This splits pnv_ioda_setup_dma() to pnv_pci_ioda1_setup_dma() and pnv_pci_ioda2_setup_dma() in order to avoid calculating DMA32 segments for PEs on PHB3. No logical changes introduced. Signed-off-by: Gavin Shan --- arch/powerpc/platforms/powernv/pci-ioda.c | 41 ++++++++++++++++++------------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 5a08e20..4c2e023 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -2383,7 +2383,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, pnv_ioda_setup_bus_dma(pe, pe->pbus); } -static void pnv_ioda_setup_dma(struct pnv_phb *phb) +static void pnv_pci_ioda1_setup_dma(struct pnv_phb *phb) { struct pci_controller *hose = phb->hose; unsigned int residual, remaining, segs, tw, base; @@ -2428,26 +2428,30 @@ static void pnv_ioda_setup_dma(struct pnv_phb *phb) segs = remaining; } - /* - * For IODA2 compliant PHB3, we needn't care about the weight. - * The all available 32-bits DMA space will be assigned to - * the specific PE. - */ - if (phb->type == PNV_PHB_IODA1) { - pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", - pe->dma_weight, segs); - pnv_pci_ioda1_setup_dma_pe(phb, pe, base, segs); - } else { - pe_info(pe, "Assign DMA32 space\n"); - segs = 0; - pnv_pci_ioda2_setup_dma_pe(phb, pe); - } + pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n", + pe->dma_weight, segs); + pnv_pci_ioda1_setup_dma_pe(phb, pe, base, segs); remaining -= segs; base += segs; } } +static void pnv_pci_ioda2_setup_dma(struct pnv_phb *phb) +{ + struct pnv_ioda_pe *pe; + + pnv_pci_ioda_setup_opal_tce_kill(phb); + + list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) { + if (!pe->dma_weight) + continue; + + pe_info(pe, "Assign DMA32 space\n"); + pnv_pci_ioda2_setup_dma_pe(phb, pe); + } +} + #ifdef CONFIG_PCI_MSI static void pnv_ioda2_msi_eoi(struct irq_data *d) { @@ -2931,10 +2935,13 @@ static void pnv_pci_ioda_setup_DMA(void) struct pnv_phb *phb; list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { - pnv_ioda_setup_dma(hose->private_data); + phb = hose->private_data; + if (phb->type == PNV_PHB_IODA1) + pnv_pci_ioda1_setup_dma(phb); + else + pnv_pci_ioda2_setup_dma(phb); /* Mark the PHB initialization done */ - phb = hose->private_data; phb->initialized = 1; } }