From patchwork Mon Nov 30 16:21:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 7727731 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 66B489F39B for ; Mon, 30 Nov 2015 16:24:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A413520558 for ; Mon, 30 Nov 2015 16:24:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1366C20562 for ; Mon, 30 Nov 2015 16:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754442AbbK3QXp (ORCPT ); Mon, 30 Nov 2015 11:23:45 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:33790 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752842AbbK3QXn (ORCPT ); Mon, 30 Nov 2015 11:23:43 -0500 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 010C75B4E1C59; Mon, 30 Nov 2015 16:23:38 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Mon, 30 Nov 2015 16:23:41 +0000 Received: from localhost (10.100.200.236) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Mon, 30 Nov 2015 16:23:41 +0000 From: Paul Burton To: CC: Paul Burton , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Michal Simek , "Jiang Liu" , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , , Russell Joyce , Arnd Bergmann , , Thomas Gleixner , "Jingoo Han" , Subject: [PATCH 06/28] PCI: xilinx: unify INTx & MSI interrupt FIFO decode Date: Mon, 30 Nov 2015 16:21:31 +0000 Message-ID: <1448900513-20856-7-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1448900513-20856-1-git-send-email-paul.burton@imgtec.com> References: <1448900513-20856-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.236] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When decoding either an INTx or MSI interrupt, the driver has no way to know which it will pull out of the interrupt FIFO. If both were pending then this would lead to either the interrupt being handled incorrectly (MSI interrupt treated as INTx) or not at all (INTx interrupt dropped by MSI path). Unify the reading of the interrupt FIFO & act according to the type of interrupt actually read. Signed-off-by: Paul Burton --- drivers/pci/host/pcie-xilinx.c | 45 +++++++++++------------------------------- 1 file changed, 12 insertions(+), 33 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index c412a37..c6fe273 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -397,7 +397,7 @@ static const struct irq_domain_ops intx_domain_ops = { static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) { struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data; - u32 val, mask, status, msi_data; + u32 val, mask, status; /* Read interrupt decode and mask registers */ val = pcie_read(port, XILINX_PCIE_REG_IDR); @@ -437,8 +437,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) xilinx_pcie_clear_err_interrupts(port); } - if (status & XILINX_PCIE_INTR_INTX) { - /* INTx interrupt received */ + if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) { + /* Interrupt received */ val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); /* Check whether interrupt valid */ @@ -447,41 +447,20 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) return IRQ_HANDLED; } - if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) { - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - /* Handle INTx Interrupt */ + if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { + irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & + XILINX_PCIE_RPIFR2_MSG_DATA; + } else { val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >> XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1; - generic_handle_irq(irq_find_mapping(port->irq_domain, - val)); + irq = irq_find_mapping(port->irq_domain, val); } - } - if (status & XILINX_PCIE_INTR_MSI) { - /* MSI Interrupt */ - val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); + /* Clear interrupt FIFO register 1 */ + pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, + XILINX_PCIE_REG_RPIFR1); - if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { - dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; - } - - if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { - msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & - XILINX_PCIE_RPIFR2_MSG_DATA; - - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - /* Handle MSI Interrupt */ - generic_handle_irq(msi_data); - } - } + generic_handle_irq(irq); } if (status & XILINX_PCIE_INTR_SLV_UNSUPP)