From patchwork Thu Dec 3 13:35:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 7760061 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EF5C0BEEE1 for ; Thu, 3 Dec 2015 13:38:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2832420513 for ; Thu, 3 Dec 2015 13:38:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4EC8B205B3 for ; Thu, 3 Dec 2015 13:38:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758761AbbLCNi0 (ORCPT ); Thu, 3 Dec 2015 08:38:26 -0500 Received: from mail-wm0-f41.google.com ([74.125.82.41]:34903 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760193AbbLCNgH (ORCPT ); Thu, 3 Dec 2015 08:36:07 -0500 Received: by wmuu63 with SMTP id u63so21386020wmu.0 for ; Thu, 03 Dec 2015 05:36:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l/x4p9Z44XCo1m9efhsGwHBvJXCDFXJ/Qy9fga1I1+A=; b=vPc3vbupvPzeZKqHSKEei0OfF1aYRrT3wkkZ7PmMZ4qT+m1zl/oQ37qLiEq5ndAAsh f+wc4xo2tU4JImnAq/lLSYoXYoRQCNA7vm3cQq7UKIwM+ZThfD/gz36+TTYfV2pkVzxw Y6Lmmb9tmF9x/PrWadqKzHFZKDQZX4CQkF8fAvGImJu9JNmxZ1LAtUBii4s2jYJ+sH3v TNHnXHC/LvX05jhgPLCsUlhlE8ldNEk2RFbTZL6aDIyZlKg9OGiS82soOYwvsP5RqJWB +jsXqB9CscFLRGKpFirtrps7WONOdlJWDZ5TuNka5FCpYZi/jI8hmD7rue+gXzKrPW+W j/Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l/x4p9Z44XCo1m9efhsGwHBvJXCDFXJ/Qy9fga1I1+A=; b=EViOTyt2BDW8GYHjoI14a/ZS0BNpxheeaoWw7xuZf4yrnQGSImWdrzCaLjrD9I5CnD TyPl3gRwJIzx5WTzBJa8ABkk0bI9E/nYl6ks1n2MQ6LmtwcmQho54Kxo+1HSwWyCj9Tx AtEhx35U466Ni+CGNWVipEmOZFgQuNL0bk8ke+I2PkNS55bKXs3egnc8ApNs+Wy34y17 PcgSOkcLqNKeCB9BWmczIY2JmeFTpISnx4TBJCeq/Oe4ofVPYG7Lb9WDpokWGcDzIbBr j0h997aYfNbhN6FC9CZvAvSbDVIx0vcsi52yW5ifQdyPxyfD/Qi7P6PY64g+/g2qPvzA I5Sw== X-Gm-Message-State: ALoCoQm2EKfjFHNlFyzBrvA1jStKgzOwPC0rujjXw3IJSlDUubDIbADqFMXts0L8uB64nGhe+Qf6 X-Received: by 10.28.143.11 with SMTP id r11mr52381823wmd.28.1449149766434; Thu, 03 Dec 2015 05:36:06 -0800 (PST) Received: from mms734.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.gmail.com with ESMTPSA id h189sm35769187wme.1.2015.12.03.05.36.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Dec 2015 05:36:05 -0800 (PST) From: Stanimir Varbanov To: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Bjorn Helgaas Cc: Srinivas Kandagatla , Rob Herring , Rob Herring , Mark Rutland , Pawel Moll , Ian Campbell , Arnd Bergmann , Jingoo Han , Pratyush Anand , Bjorn Andersson , Stanimir Varbanov Subject: [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region Date: Thu, 3 Dec 2015 15:35:20 +0200 Message-Id: <1449149725-27607-2-git-send-email-stanimir.varbanov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1449149725-27607-1-git-send-email-stanimir.varbanov@linaro.org> References: <1449149725-27607-1-git-send-email-stanimir.varbanov@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID,T_RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add 'write memory' barrier after enable region in PCIE_ATU_CR2 register. The barrier is needed to ensure that the region enable request has been reached it's destination at time when we read/write to PCI configuration space. Without this barrier PCI device enumeration during kernel boot is not reliable, and reading configuration space for particular PCI device on the bus returns zero aka no device. Signed-off-by: Stanimir Varbanov --- drivers/pci/host/pcie-designware.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 02a7452bdf23..ed4dc2e2553b 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -164,6 +164,11 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); + /* + * ensure that the ATU enable has been happaned before accessing + * pci configuration/io spaces through dw_pcie_cfg_[read|write]. + */ + wmb(); } static struct irq_chip dw_msi_irq_chip = {