From patchwork Wed Jan 6 10:59:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 7967111 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 634C39F1C0 for ; Wed, 6 Jan 2016 11:00:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 718E72017D for ; Wed, 6 Jan 2016 11:00:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 71AA620172 for ; Wed, 6 Jan 2016 11:00:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753655AbcAFK7w (ORCPT ); Wed, 6 Jan 2016 05:59:52 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:50571 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753335AbcAFK7f (ORCPT ); Wed, 6 Jan 2016 05:59:35 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u06AxOH2014491; Wed, 6 Jan 2016 04:59:24 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u06AxOfW026622; Wed, 6 Jan 2016 04:59:24 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Wed, 6 Jan 2016 04:59:23 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u06AxB7k018319; Wed, 6 Jan 2016 04:59:20 -0600 From: Kishon Vijay Abraham I To: CC: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , , , , , , Subject: [PATCH 2/2] phy: ti-pipe3: configure usb3 phy to be used as pcie phy Date: Wed, 6 Jan 2016 16:29:08 +0530 Message-ID: <1452077948-26232-3-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1452077948-26232-1-git-send-email-kishon@ti.com> References: <1452077948-26232-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DRA72 uses USB3 PHY for the 2nd lane of PCIE. The configuration required to make USB3 PHY used for the 2nd lane of PCIe is done here. Signed-off-by: Kishon Vijay Abraham I Acked-by: Rob Herring --- Documentation/devicetree/bindings/phy/ti-phy.txt | 2 ++ drivers/phy/phy-ti-pipe3.c | 30 +++++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index a3b3945..6a7de94 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -91,6 +91,8 @@ Optional properties: register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. - syscon-pcs : phandle/offset pair. Phandle to the system control module and the register offset to write the PCS delay value. + - "ti,configure-as-pcie" : property to indicate if the PHY should be + configured as PCIE PHY. Deprecated properties: - ctrl-module : phandle of the control module used by PHY driver to power on diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c index 7d83d2b..793185e 100644 --- a/drivers/phy/phy-ti-pipe3.c +++ b/drivers/phy/phy-ti-pipe3.c @@ -56,6 +56,12 @@ #define SATA_PLL_SOFT_RESET BIT(18) +#define PHY_RX_ANA_PRGRAMMABILITY_REG 0xC +#define MEM_EN_PLLBYP BIT(7) + +#define PHY_TX_TEST_CONFIG 0x2C +#define MEM_ENTESTCLK BIT(31) + #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14 @@ -68,6 +74,10 @@ #define PCIE_PCS_MASK 0xFF0000 #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10 +#define PIPE3_PHY_DISABLE_SYNC_POWER BIT(4) + +#define CONFIGURE_AS_PCIE BIT(0) + /* * This is an Empirical value that works, need to confirm the actual * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status @@ -90,6 +100,7 @@ struct pipe3_dpll_map { }; struct ti_pipe3 { + u32 flags; void __iomem *pll_ctrl_base; void __iomem *phy_rx; void __iomem *phy_tx; @@ -270,6 +281,19 @@ static int ti_pipe3_init(struct phy *x) int ret = 0; ti_pipe3_enable_clocks(phy); + + if (phy->flags & CONFIGURE_AS_PCIE) { + val = ti_pipe3_readl(phy->phy_rx, + PHY_RX_ANA_PRGRAMMABILITY_REG); + val |= MEM_EN_PLLBYP; + ti_pipe3_writel(phy->phy_rx, PHY_RX_ANA_PRGRAMMABILITY_REG, + val); + val = ti_pipe3_readl(phy->phy_tx, PHY_TX_TEST_CONFIG); + val |= MEM_ENTESTCLK; + ti_pipe3_writel(phy->phy_tx, PHY_TX_TEST_CONFIG, val); + return 0; + } + /* * Set pcie_pcs register to 0x96 for proper functioning of phy * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table @@ -318,7 +342,8 @@ static int ti_pipe3_exit(struct phy *x) return 0; /* PCIe doesn't have internal DPLL */ - if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) { + if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie") && + !(phy->flags & CONFIGURE_AS_PCIE)) { /* Put DPLL in IDLE mode */ val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); val |= PLL_IDLE; @@ -590,6 +615,9 @@ static int ti_pipe3_probe(struct platform_device *pdev) if (ret) return ret; + if (of_property_read_bool(node, "ti,configure-as-pcie")) + phy->flags |= CONFIGURE_AS_PCIE; + platform_set_drvdata(pdev, phy); pm_runtime_enable(dev);