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[3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

Message ID 1452576399-1513-4-git-send-email-bharatku@xilinx.com (mailing list archive)
State New, archived
Delegated to: Bjorn Helgaas
Headers show

Commit Message

Bharat Kumar Gogada Jan. 12, 2016, 5:26 a.m. UTC
Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
Zynq and Microblaze Architectures.
With these modifications drivers/pci/host/pcie-xilinx.c, will
work on both Zynq and Microblaze Architectures.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Changed Total number of MSI IRQ count logic according to both architectures.
Updated MSI assigning functions accordingly to new count.
Modified irq_domain_add_linear with new MSI IRQ count.
Added #ifdef to pci_fixup_irqs which are ARM specific API.
---
 drivers/pci/host/pcie-xilinx.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)
diff mbox

Patch

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3e3757f..05f6f2e 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -93,6 +93,11 @@ 
 
 /* Number of MSI IRQs */
 #define XILINX_NUM_MSI_IRQS		128
+#ifdef CONFIG_ARM
+#define TOT_NR_IRQS			XILINX_NUM_MSI_IRQS
+#else
+#define TOT_NR_IRQS			(NR_IRQS + XILINX_NUM_MSI_IRQS)
+#endif
 
 
 /**
@@ -238,15 +243,20 @@  static void xilinx_pcie_destroy_msi(unsigned int irq)
  */
 static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
 {
+	int irq;
 	int pos;
 
 	pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
-	if (pos < XILINX_NUM_MSI_IRQS)
+	irq = pos;
+#ifdef CONFIG_MICROBLAZE
+	irq = XILINX_NUM_MSI_IRQS + pos;
+#endif
+	if (irq < TOT_NR_IRQS)
 		set_bit(pos, msi_irq_in_use);
 	else
 		return -ENOSPC;
 
-	return pos;
+	return irq;
 }
 
 /**
@@ -520,7 +530,7 @@  static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
 
 		free_pages(port->msi_pages, 0);
 
-		num_irqs = XILINX_NUM_MSI_IRQS;
+		num_irqs = TOT_NR_IRQS;
 	} else {
 		/* INTx */
 		num_irqs = 4;
@@ -565,7 +575,7 @@  static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
 	/* Setup MSI */
 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
 		port->irq_domain = irq_domain_add_linear(node,
-							 XILINX_NUM_MSI_IRQS,
+							 TOT_NR_IRQS,
 							 &msi_domain_ops,
 							 &xilinx_pcie_msi_chip);
 		if (!port->irq_domain) {
@@ -705,7 +715,9 @@  static int xilinx_pcie_probe(struct platform_device *pdev)
 #endif
 	pci_scan_child_bus(bus);
 	pci_assign_unassigned_bus_resources(bus);
+#ifdef CONFIG_ARM
 	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+#endif
 	pci_bus_add_devices(bus);
 	platform_set_drvdata(pdev, port);