From patchwork Tue Jan 12 17:36:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Kumar Gogada X-Patchwork-Id: 8019761 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A49089F3F6 for ; Tue, 12 Jan 2016 17:38:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B69CC203F4 for ; Tue, 12 Jan 2016 17:38:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C6B5C203B7 for ; Tue, 12 Jan 2016 17:38:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760197AbcALRi0 (ORCPT ); Tue, 12 Jan 2016 12:38:26 -0500 Received: from mail-sn1nam02on0053.outbound.protection.outlook.com ([104.47.36.53]:20393 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752203AbcALRgm (ORCPT ); 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Tue, 12 Jan 2016 09:36:36 -0800 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1aJ2s0-0006MI-E2; Tue, 12 Jan 2016 09:36:36 -0800 Received: from xsj-pvapsmtp01 (mailhost.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u0CHaYdr024369; Tue, 12 Jan 2016 09:36:34 -0800 Received: from [172.23.64.208] (helo=xhdrdevl6.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1aJ2rx-0006Lj-U3; Tue, 12 Jan 2016 09:36:34 -0800 Received: by xhdrdevl6.xilinx.com (Postfix, from userid 45489) id 171A3F2000F; Tue, 12 Jan 2016 23:06:33 +0530 (IST) From: Bharat Kumar Gogada To: , , , , , , , , , , , , , , CC: , , , , "Bharat Kumar Gogada" , Ravi Kiran Gummaluri Subject: [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Tue, 12 Jan 2016 23:06:11 +0530 Message-ID: <1452620173-4905-4-git-send-email-bharatku@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> References: <1452620173-4905-1-git-send-email-bharatku@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22060.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83; 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PCL:0; RULEID:(601004)(2401047)(8121501046)(520078)(13018025)(5005006)(13015025)(13017025)(10201501046)(3002001); SRVR:CY1NAM02HT198; BCL:0; PCL:0; RULEID:; SRVR:CY1NAM02HT198; X-Forefront-PRVS: 081904387B X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2016 17:36:37.2692 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT198 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both Zynq and Microblaze Architectures. With these modifications drivers/pci/host/pcie-xilinx.c, will work on both Zynq and Microblaze Architectures. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri --- Changes: Changed Total number of MSI IRQ count logic according to both architectures. Updated MSI assigning functions accordingly to new count. Modified irq_domain_add_linear with new MSI IRQ count. Added #ifdef to pci_fixup_irqs which is ARM specific API. --- drivers/pci/host/pcie-xilinx.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 3e3757f..1981948 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -92,7 +92,12 @@ #define ECAM_DEV_NUM_SHIFT 12 /* Number of MSI IRQs */ -#define XILINX_NUM_MSI_IRQS 128 +#define XILINX_NUM_MSI_IRQS 128 +#ifdef CONFIG_ARM +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS +#else +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) +#endif /** @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq) */ static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) { + int irq; int pos; pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); - if (pos < XILINX_NUM_MSI_IRQS) + irq = pos; +#ifdef CONFIG_MICROBLAZE + irq = XILINX_NUM_MSI_IRQS + pos; +#endif + if (irq < TOT_NR_IRQS) set_bit(pos, msi_irq_in_use); else return -ENOSPC; - return pos; + return irq; } /** @@ -520,7 +530,7 @@ static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port) free_pages(port->msi_pages, 0); - num_irqs = XILINX_NUM_MSI_IRQS; + num_irqs = TOT_NR_IRQS; } else { /* INTx */ num_irqs = 4; @@ -565,7 +575,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) /* Setup MSI */ if (IS_ENABLED(CONFIG_PCI_MSI)) { port->irq_domain = irq_domain_add_linear(node, - XILINX_NUM_MSI_IRQS, + TOT_NR_IRQS, &msi_domain_ops, &xilinx_pcie_msi_chip); if (!port->irq_domain) { @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev) #endif pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); +#ifdef CONFIG_ARM pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); +#endif pci_bus_add_devices(bus); platform_set_drvdata(pdev, port);