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Lian" X-Patchwork-Id: 8187581 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4E0B2BEEE5 for ; Tue, 2 Feb 2016 09:02:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 756182027D for ; Tue, 2 Feb 2016 09:01:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1B69520279 for ; Tue, 2 Feb 2016 09:01:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754131AbcBBJBy (ORCPT ); Tue, 2 Feb 2016 04:01:54 -0500 Received: from mail-by2on0089.outbound.protection.outlook.com ([207.46.100.89]:12455 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753962AbcBBJBx (ORCPT ); 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Tue, 2 Feb 2016 08:29:01 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.20]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id u128Suc8025218; Tue, 2 Feb 2016 01:28:57 -0700 From: Minghuan Lian To: CC: , Roy Zang , Mingkai Hu , Stuart Yoder , Yang-Leo Li , Arnd Bergmann , "Bjorn Helgaas" , Minghuan Lian Subject: [PATCH 1/4] ARM: dts: ls1021a: add PCIe dts node Date: Tue, 2 Feb 2016 16:30:07 +0800 Message-ID: <1454401807-28751-1-git-send-email-Minghuan.Lian@nxp.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Matching-Connectors: 130988753413475240; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11OLC013; 1:JiKl6pzgpgao6K+idX90QYNPHvT9mNyJs62sn/GT8902raI/w1cfq4TDHA/gZ8e6w5pU8kBxFdDtyD2sKa+c1m6k9x3qyisrh0hKHhY9kKaG4hwnm4wEV3bo+2SyzxVBM9vW1Vw28686NUWnXR5GJg6DVri0LjaplvbTCgeRj/wH9RiSyr4mstEomQR/QykJxK7SKe2hJe+J0hezQdK+hMJYwAgtIdtPbBOcosmrjlyuFbfPi6SweRYHAcsMnOxMu2FcTxR9H9/oYAcIXEdEv1Qiyn7jz0HhUhw9U3Nl7zRDo5EnipDhf8uqASBfUVrA5qoha0f7EVD+fDnBwO5feCgb+UPdp75zhVorIyid//iNzTHS+oNV3szQ9ldB4xEV5twiJrKMsidP8L61LqAhlMzN3RjgvpCsJxKfhkjnHeKtlBRtEEdOmAGu/jMZETN9fJ9CJfKPjW5Vy9vFZR4norajY+2ClmNrQgJf8HSTWn/JvEIUSLc8YAlIkAWqkl0E2L3vWgL7wguBMK3rTfOfneu1UcKjzZDQxoXbSF/Oq1ovZzn5WumM6s6dQxdcsIefpo5jSy5B8y7ixGRcSDj4MQ== X-Forefront-Antispam-Report: CIP:192.88.168.50; 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The patch adds their node to dts file. Signed-off-by: Minghuan Lian --- arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 2c84ca2..274d647 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -560,5 +560,49 @@ dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; }; + + pcie@3400000 { + compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = ; /* controller interrupt */ + fsl,pcie-scfg = <&scfg 0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + }; + + pcie@3500000 { + compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = ; + fsl,pcie-scfg = <&scfg 1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + }; }; };