From patchwork Mon Feb 8 00:00:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Gortmaker X-Patchwork-Id: 8245881 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 20A3ABEEE5 for ; Mon, 8 Feb 2016 00:02:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 16F7220173 for ; Mon, 8 Feb 2016 00:02:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 28EB6201E4 for ; Mon, 8 Feb 2016 00:02:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755105AbcBHACD (ORCPT ); Sun, 7 Feb 2016 19:02:03 -0500 Received: from mail1.windriver.com ([147.11.146.13]:62564 "EHLO mail1.windriver.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755088AbcBHACB (ORCPT ); Sun, 7 Feb 2016 19:02:01 -0500 Received: from ALA-HCA.corp.ad.wrs.com (ala-hca.corp.ad.wrs.com [147.11.189.40]) by mail1.windriver.com (8.15.2/8.15.1) with ESMTPS id u1801ABC023934 (version=TLSv1 cipher=AES128-SHA bits=128 verify=FAIL); Sun, 7 Feb 2016 16:01:10 -0800 (PST) Received: from yow-lpgnfs-02.corp.ad.wrs.com (128.224.149.8) by ALA-HCA.corp.ad.wrs.com (147.11.189.40) with Microsoft SMTP Server id 14.3.248.2; Sun, 7 Feb 2016 16:01:09 -0800 From: Paul Gortmaker To: CC: Paul Gortmaker , Murali Karicheri , Bjorn Helgaas , Stanimir Varbanov , Geert Uytterhoeven , Thierry Reding , Arnd Bergmann , , Subject: [PATCH 4/5] drivers/pci: make host/pci-keystone-dw.c modular Date: Sun, 7 Feb 2016 19:00:43 -0500 Message-ID: <1454889644-27830-5-git-send-email-paul.gortmaker@windriver.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1454889644-27830-1-git-send-email-paul.gortmaker@windriver.com> References: <1454889644-27830-1-git-send-email-paul.gortmaker@windriver.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Export the symbols that this driver requires in order for it to be modular. In addition to the one use case of a dw_pci sym, it has many instances of its own ks_dw_pci syms that need exporting in order to modpost w/o error. Cc: Murali Karicheri Cc: Bjorn Helgaas Cc: Stanimir Varbanov Cc: Geert Uytterhoeven Cc: Thierry Reding Cc: Arnd Bergmann Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Paul Gortmaker --- drivers/pci/host/Kconfig | 2 +- drivers/pci/host/pci-keystone-dw.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 75a605426538..b040ad7ba44d 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -69,7 +69,7 @@ config PCIE_SPEAR13XX Say Y here if you want PCIe support on SPEAr13XX SoCs. config PCI_KEYSTONE - bool "TI Keystone PCIe controller" + tristate "TI Keystone PCIe controller" depends on ARCH_KEYSTONE select PCIE_DW select PCIEPORTBUS diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c index ed34c9520a02..f1550a8d2e29 100644 --- a/drivers/pci/host/pci-keystone-dw.c +++ b/drivers/pci/host/pci-keystone-dw.c @@ -76,6 +76,7 @@ phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp) return ks_pcie->app.start + MSI_IRQ; } +EXPORT_SYMBOL(ks_dw_pcie_get_msi_addr); void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) { @@ -99,6 +100,7 @@ void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) } } } +EXPORT_SYMBOL(ks_dw_pcie_handle_msi_irq); static void ks_dw_pcie_msi_irq_ack(struct irq_data *d) { @@ -127,6 +129,7 @@ void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) writel(BIT(bit_pos), ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4)); } +EXPORT_SYMBOL(ks_dw_pcie_msi_set_irq); void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) { @@ -137,6 +140,7 @@ void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) writel(BIT(bit_pos), ks_pcie->va_app_base + MSI0_IRQ_ENABLE_CLR + (reg_offset << 4)); } +EXPORT_SYMBOL(ks_dw_pcie_msi_clear_irq); static void ks_dw_pcie_msi_irq_mask(struct irq_data *d) { @@ -220,6 +224,7 @@ int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip) return 0; } +EXPORT_SYMBOL(ks_dw_pcie_msi_host_init); void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) { @@ -228,6 +233,7 @@ void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) for (i = 0; i < MAX_LEGACY_IRQS; i++) writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4)); } +EXPORT_SYMBOL(ks_dw_pcie_enable_legacy_irqs); void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset) { @@ -247,6 +253,7 @@ void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset) /* EOI the INTx interrupt */ writel(offset, ks_pcie->va_app_base + IRQ_EOI); } +EXPORT_SYMBOL(ks_dw_pcie_handle_legacy_irq); static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d) { @@ -347,6 +354,7 @@ void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS), ks_pcie->va_app_base + CMD_STATUS); } +EXPORT_SYMBOL(ks_dw_pcie_setup_rc_app_regs); /** * ks_pcie_cfg_setup() - Set up configuration space address for a device @@ -400,6 +408,7 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, return dw_pcie_cfg_read(addr + where, size, val); } +EXPORT_SYMBOL(ks_dw_pcie_rd_other_conf); int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) @@ -412,6 +421,7 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, return dw_pcie_cfg_write(addr + where, size, val); } +EXPORT_SYMBOL(ks_dw_pcie_wr_other_conf); /** * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization @@ -437,6 +447,7 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) */ writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0); } +EXPORT_SYMBOL(ks_dw_pcie_v3_65_scan_bus); /** * ks_dw_pcie_link_up() - Check if link up @@ -447,6 +458,7 @@ int ks_dw_pcie_link_up(struct pcie_port *pp) return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; } +EXPORT_SYMBOL(ks_dw_pcie_link_up); void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) { @@ -461,6 +473,7 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) val = readl(ks_pcie->va_app_base + CMD_STATUS); writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS); } +EXPORT_SYMBOL(ks_dw_pcie_initiate_link_train); /** * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware @@ -469,7 +482,7 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) * and call dw_pcie_v3_65_host_init() API to initialize the Keystone * PCI host controller. */ -int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, +int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, struct device_node *msi_intc_np) { struct pcie_port *pp = &ks_pcie->pp; @@ -510,3 +523,4 @@ int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, return dw_pcie_host_init(pp); } +EXPORT_SYMBOL(ks_dw_pcie_host_init);