From patchwork Thu Feb 11 16:28:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Kumar Gogada X-Patchwork-Id: 8282621 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C9ACFBEEE5 for ; Thu, 11 Feb 2016 16:29:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C119D203C1 for ; Thu, 11 Feb 2016 16:29:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 98E63203B5 for ; Thu, 11 Feb 2016 16:29:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750771AbcBKQ2e (ORCPT ); Thu, 11 Feb 2016 11:28:34 -0500 Received: from mail-sn1nam02on0070.outbound.protection.outlook.com ([104.47.36.70]:44155 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751367AbcBKQ22 (ORCPT ); Thu, 11 Feb 2016 11:28:28 -0500 Received: from CY1NAM02FT034.eop-nam02.prod.protection.outlook.com (10.152.74.57) by CY1NAM02HT200.eop-nam02.prod.protection.outlook.com (10.152.74.240) with Microsoft SMTP Server (TLS) id 15.1.409.7; Thu, 11 Feb 2016 16:28:26 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; york.ac.uk; dkim=none (message not signed) header.d=none;york.ac.uk; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; Received: from xsj-pvapsmtpgw02 (149.199.60.100) by CY1NAM02FT034.mail.protection.outlook.com (10.152.75.190) with Microsoft SMTP Server (TLS) id 15.1.409.7 via Frontend Transport; Thu, 11 Feb 2016 16:28:25 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66]:34001 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw02 with esmtp (Exim 4.63) (envelope-from ) id 1aTu6S-0000h8-8h; Thu, 11 Feb 2016 08:28:24 -0800 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1aTu6S-0006h5-3e; Thu, 11 Feb 2016 08:28:24 -0800 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u1BGSHVA001161; Thu, 11 Feb 2016 08:28:18 -0800 Received: from [172.23.64.208] (helo=xhdrdevl6.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1aTu6L-0006fr-9T; Thu, 11 Feb 2016 08:28:17 -0800 Received: by xhdrdevl6.xilinx.com (Postfix, from userid 45489) id 75FD4F2001A; Thu, 11 Feb 2016 21:58:16 +0530 (IST) From: Bharat Kumar Gogada To: , , , , , , , , , , , , , , CC: , , , , "Bharat Kumar Gogada" , Ravi Kiran Gummaluri Subject: [PATCH V4 2/5] PCI: xilinx: Removing struct hw_pci structure. Date: Thu, 11 Feb 2016 21:58:08 +0530 Message-ID: <1455208091-15556-3-git-send-email-bharatku@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1455208091-15556-1-git-send-email-bharatku@xilinx.com> References: <1455208091-15556-1-git-send-email-bharatku@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22124.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(438002)(189002)(199003)(90966002)(106466001)(48376002)(5001770100001)(52956003)(1220700001)(6806005)(5001960100002)(2906002)(189998001)(107886002)(5008740100001)(11100500001)(586003)(4001430100002)(47776003)(5003940100001)(4326007)(2201001)(1096002)(86362001)(76176999)(63266004)(36386004)(19580405001)(92566002)(2950100001)(19580395003)(87936001)(50986999)(36756003)(42186005)(45336002)(103686003)(50466002)(50226001)(229853001)(46386002)(33646002)(921003)(107986001)(2101003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1NAM02HT200; H:xsj-pvapsmtpgw02; FPR:; SPF:Pass; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 718fdd41-157e-443e-405d-08d333005e1a X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(8251501002); SRVR:CY1NAM02HT200; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(13024025)(5005006)(13017025)(13023025)(13015025)(8121501046)(13018025)(10201501046)(3002001); SRVR:CY1NAM02HT200; BCL:0; PCL:0; RULEID:; SRVR:CY1NAM02HT200; X-Forefront-PRVS: 08497C3D99 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2016 16:28:25.1294 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT200 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Removing struct hw_pci and adding generic PCI core API's. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri Reviewed-by: Arnd Bergmann --- Changes: Removing architecure dependecy structure struct hw_pci which is ARM 32-bit specific structure, and adding generic PCI core API's to register to PCI subsytem. Removing funtions which are not being used with generic API's. --- drivers/pci/host/pcie-xilinx.c | 82 +++++++++--------------------------------- 1 file changed, 16 insertions(+), 66 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 627878d..13fec35 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -111,17 +111,11 @@ struct xilinx_pcie_port { u8 root_busno; struct device *dev; struct irq_domain *irq_domain; - struct resource bus_range; struct list_head resources; }; static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS); -static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys) -{ - return sys->private_data; -} - static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg) { return readl(port->reg_base + reg); @@ -163,7 +157,7 @@ static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port) */ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) { - struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata); + struct xilinx_pcie_port *port = bus->sysdata; /* Check if link is up when trying to access downstream ports */ if (bus->number != port->root_busno) @@ -196,7 +190,7 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { - struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata); + struct xilinx_pcie_port *port = bus->sysdata; int relbus; if (!xilinx_pcie_valid_device(bus, devfn)) @@ -228,7 +222,7 @@ static void xilinx_pcie_destroy_msi(unsigned int irq) if (!test_bit(irq, msi_irq_in_use)) { msi = irq_get_msi_desc(irq); - port = sys_to_pcie(msi_desc_to_pci_sysdata(msi)); + port = msi_desc_to_pci_sysdata(msi); dev_err(port->dev, "Trying to free unused MSI#%d\n", irq); } else { clear_bit(irq, msi_irq_in_use); @@ -277,7 +271,7 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, struct msi_desc *desc) { - struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata); + struct xilinx_pcie_port *port = pdev->bus->sysdata; unsigned int irq; int hwirq; struct msi_msg msg; @@ -614,47 +608,6 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port) } /** - * xilinx_pcie_setup - Setup memory resources - * @nr: Bus number - * @sys: Per controller structure - * - * Return: '1' on success and error value on failure - */ -static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys) -{ - struct xilinx_pcie_port *port = sys_to_pcie(sys); - - list_splice_init(&port->resources, &sys->resources); - - return 1; -} - -/** - * xilinx_pcie_scan_bus - Scan PCIe bus for devices - * @nr: Bus number - * @sys: Per controller structure - * - * Return: Valid Bus pointer on success and NULL on failure - */ -static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys) -{ - struct xilinx_pcie_port *port = sys_to_pcie(sys); - struct pci_bus *bus; - - port->root_busno = sys->busnr; - - if (IS_ENABLED(CONFIG_PCI_MSI)) - bus = pci_scan_root_bus_msi(port->dev, sys->busnr, - &xilinx_pcie_ops, sys, - &sys->resources, - &xilinx_pcie_msi_chip); - else - bus = pci_scan_root_bus(port->dev, sys->busnr, - &xilinx_pcie_ops, sys, &sys->resources); - return bus; -} - -/** * xilinx_pcie_parse_dt - Parse Device tree * @port: PCIe port information * @@ -704,8 +657,9 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port) static int xilinx_pcie_probe(struct platform_device *pdev) { struct xilinx_pcie_port *port; - struct hw_pci hw; struct device *dev = &pdev->dev; + struct pci_bus *bus; + int err; resource_size_t iobase = 0; LIST_HEAD(res); @@ -739,24 +693,20 @@ static int xilinx_pcie_probe(struct platform_device *pdev) dev_err(dev, "Getting bridge resources failed\n"); return err; } - - platform_set_drvdata(pdev, port); - - /* Register the device */ - memset(&hw, 0, sizeof(hw)); - hw = (struct hw_pci) { - .nr_controllers = 1, - .private_data = (void **)&port, - .setup = xilinx_pcie_setup, - .map_irq = of_irq_parse_and_map_pci, - .scan = xilinx_pcie_scan_bus, - .ops = &xilinx_pcie_ops, - }; + bus = pci_create_root_bus(&pdev->dev, 0, + &xilinx_pcie_ops, port, &res); + if (!bus) + return -ENOMEM; #ifdef CONFIG_PCI_MSI xilinx_pcie_msi_chip.dev = port->dev; + bus->msi = &xilinx_pcie_msi_chip; #endif - pci_common_init_dev(dev, &hw); + pci_scan_child_bus(bus); + pci_assign_unassigned_bus_resources(bus); + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); + pci_bus_add_devices(bus); + platform_set_drvdata(pdev, port); return 0; }