From patchwork Tue Mar 8 15:48:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 8535451 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 48D249F46A for ; Tue, 8 Mar 2016 15:48:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6F25E2014A for ; Tue, 8 Mar 2016 15:48:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8543720131 for ; Tue, 8 Mar 2016 15:48:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752969AbcCHPsV (ORCPT ); Tue, 8 Mar 2016 10:48:21 -0500 Received: from mail-pa0-f43.google.com ([209.85.220.43]:33850 "EHLO mail-pa0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752435AbcCHPsU (ORCPT ); Tue, 8 Mar 2016 10:48:20 -0500 Received: by mail-pa0-f43.google.com with SMTP id fy10so15112860pac.1; Tue, 08 Mar 2016 07:48:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=9JHveWT4vtf00pjfW7vYkJjz6AAscuJC2VRytubfgos=; b=dQgtmz49JlkdUqfYoVWSY4/adU+Icm11ytwhkr7UdvGMv498V/wTxpEX5wNx0M+Kkt c8RYk2YUXSiUHWwCrjlW+7nEB70B0fnEElTywVVFnczNTXYoPpzYSKXErsUzMxq1jv+5 pFNcoVFHCOy0iuV8Ugx6mjSUuOXCrCJzS7xXLhMOMSDXyoesNMK+kYm20K3Vk58zork1 Os8VWRzE11ho5BqfpmbnKxTqPU4UH/lIHazrEP+dCfHregWQdoTOhiyv/hGzAgk5f33B GQRinZrWdlHd1IbbRMB03PsnE+F1l8LGS6AewXA+reUZKo3aUgZw/Uy2PHOXjIuktcC5 w1tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=9JHveWT4vtf00pjfW7vYkJjz6AAscuJC2VRytubfgos=; b=N7eeOBWJ+l8+i78UPTCm79A4WAFjuQ1Bv2rlJbVXYBdq4a+rH77qyWCCYjjihYWBTJ BOu+1i/Od5r0273Nz3LWQmARYZoyxg1j3IBh/9WgHZ8lgd0pDQ58UYOIbXs+aY7gsLSr XdM3UO7RiS8tbTmqw8R8SLq5Gn8t5ijTHYmSa3n+1yqCU5AIa8mWDIOjk8WgZboY7nGR VcjrDrfkPWoWNyQ6jyMTgAxs8+wnUxnT3B4aIMgndEFNwya8faNimscLMCAx4XH2HHnf eEtJffPi9N10boFdRvAFtBMf/9bE9aipqvQg61vZ7dLJd4OC8btkzjOILDQugLcPv03I sjCQ== X-Gm-Message-State: AD7BkJJE7NtR8xw0Qs+rdZ2m6oT92Rp3d+pNukDpPYUz7RYf2iaZSQf5zjVmGNaXvozM3w== X-Received: by 10.66.218.225 with SMTP id pj1mr42176458pac.83.1457452099363; Tue, 08 Mar 2016 07:48:19 -0800 (PST) Received: from localhost (port-3654.pppoe.wtnet.de. [84.46.14.84]) by smtp.gmail.com with ESMTPSA id 27sm5902914pfo.58.2016.03.08.07.48.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Mar 2016 07:48:18 -0800 (PST) From: Thierry Reding To: Bjorn Helgaas Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Alexandre Courbot , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs Date: Tue, 8 Mar 2016 16:48:13 +0100 Message-Id: <1457452094-5409-1-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.7.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Changes to the pad controller device tree binding have required that each lane be associated with a separate PHY. Update the PCI host bridge device tree binding to allow each root port to define the list of PHYs required to drive the lanes associated with it. Signed-off-by: Thierry Reding Acked-by: Rob Herring --- .../devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index 75321ae23c08..033fe4b5afac 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -60,11 +60,14 @@ Required properties: - afi - pcie_x -Required properties on Tegra124 and later: +Required properties on Tegra124 and later (deprecated): - phys: Must contain an entry for each entry in phy-names. - phy-names: Must include the following entries: - pcie +These properties are deprecated in favour of per-lane PHYs define in each of +the root ports (see below). + Power supplies for Tegra20: - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. @@ -122,6 +125,13 @@ Required properties: - Root port 0 uses 4 lanes, root port 1 is unused. - Both root ports use 2 lanes. +Required properties for Tegra124 and later: +- phys: Must contain an phandle to a PHY for each entry in phy-names. +- phy-names: Must include an entry for each active lane. Note that the number + of entries does not have to (though usually will) be equal to the specified + number of lanes in the nvidia,num-lanes property. Entries are of the form + "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes. + Example: SoC DTSI: @@ -169,6 +179,9 @@ SoC DTSI: ranges; nvidia,num-lanes = <2>; + + phys = <&{/padctl@0,7009f000/pads/pcie/pcie-4}>; + phy-names = "pcie-0"; }; pci@2,0 { @@ -183,6 +196,9 @@ SoC DTSI: ranges; nvidia,num-lanes = <2>; + + phys = <&{/padctl@0,7009f000/pads/pcie/pcie-2}>; + phy-names = "pcie-0"; }; };