From patchwork Wed Apr 6 23:14:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 8767131 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 593DBC0553 for ; Wed, 6 Apr 2016 23:12:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5A1DF201BB for ; Wed, 6 Apr 2016 23:12:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 27210201ED for ; Wed, 6 Apr 2016 23:12:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754538AbcDFXMS (ORCPT ); Wed, 6 Apr 2016 19:12:18 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:32781 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754364AbcDFXMR (ORCPT ); Wed, 6 Apr 2016 19:12:17 -0400 Received: by mail-pa0-f54.google.com with SMTP id zm5so42007665pac.0 for ; Wed, 06 Apr 2016 16:12:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gateworks-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=rnd0JxJeDGJ/rbGx+rOMUFEK0yKaFezwfvNKK19FiVE=; b=X38Kb0ni5VZUpF7GJ4nideAk2EpXZhei91B27x2ltUkRJ2EfSuzbnSvH/pOA0oQlI8 oFSl/Ni1bLmu7zxheL//JkMUKnaxTzeZl3JKU7P2BVUukALvh77FLJR4nHICuWiVwz3K vyTXYBsNKKfarM5gg9VoczKb4DaqdmooY9QZCUgU24ley6sPSfG7TP7sWFEmo2aN/EQc AyVzmwe0HheBPivBuPk4a/FrotOY8GMRXcqWeZ4n01gLOtnR+JSsPZM8Q7u3ZwH4JHCE jiyQ11sbeHZXWf+GFst1nJnilWXSqyBU12fXJE86Eq+Q/I3Z/hN7q/0duyD51I3diej0 a7Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=rnd0JxJeDGJ/rbGx+rOMUFEK0yKaFezwfvNKK19FiVE=; b=nAstsQn5frxKKg/4y9bhLWYy9fwmMZbEnD5+Y93OxWlO54cUbs6hc8DCasYYxx2zAO PBa2mouejptUNfrqPSsHx6OGOekOKDsElhL6Nx4FWsEFt/Runhns4f/sGWaER5HKNasX j58Gwqg3lKQDDr44xnPV9QulLzMocXr2HPsd0Sk4gd8kGTc2tC+E0sR993siSX87txMl 8mJWAMC/77Uy86qbaqyE6XIZHwrM07yIDFZiYhfdfqbV/3+ifoaK9szhOHfpkcA2BavW sIEad8Jw/Ii8/DDPX3ygiSJT/IsxPMXL7VhMaB5shDmbf63jrjkxCeEQqBc2YDXdrmXM mrpg== X-Gm-Message-State: AD7BkJLhv01wSuAjGGDKb94C1Sit7b8P5GcgoMPTD6cZ+0hey3VXLqA/gGs31GONIxO0JA== X-Received: by 10.67.21.205 with SMTP id hm13mr74839352pad.56.1459984336440; Wed, 06 Apr 2016 16:12:16 -0700 (PDT) Received: from tharvey.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by smtp.gmail.com with ESMTPSA id p26sm7247229pfi.84.2016.04.06.16.12.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 Apr 2016 16:12:15 -0700 (PDT) From: Tim Harvey To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, Lucas Stach , Fabio Estevam , Zhu Richard , Akshay Bhat , Rob Herring , Shawn Guo Subject: [PATCH v5] PCI: imx6: add dt prop for link gen, default to gen1 Date: Wed, 6 Apr 2016 16:14:54 -0700 Message-Id: <1459984494-15782-1-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.9.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Freescale has stated [1] that the LVDS clock source of the IMX6 does not pass the PCI Gen2 clock jitter test, therefore unless an external Gen2 compliant external clock source is present and supplied back to the IMX6 PCIe core via LVDS CLK1/CLK2 you can not claim Gen2 compliance. Add a dt property to specify gen1 vs gen2 and check this before allowing a Gen2 link. We default to Gen1 if the property is not present because at this time there are no IMX6 boards in mainline that 'input' a clock on LVDS CLK1/CLK2. In order to be Gen2 compliant on IMX6 you need to: - have a Gen2 compliant external clock generator and route that clock back to either LVDS CLK1 or LVDS CLK2 as an input. (see IMX6SX-SabreSD reference design) - specify this clock in the pcie node in the dt (ie IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output) [1] https://community.freescale.com/message/453209 Cc: Lucas Stach Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Zhu Richard Cc: Akshay Bhat Cc: Rob Herring Cc: Shawn Guo Signed-off-by: Tim Harvey Reviewed-by: Lucas Stach --- v5: - clearly default link gen to 1 when dt prop is read to avoid confusion v4: - rebase against linux-pci/master - add fsl vendor prefix to dt prop v3: - added note in dt bindings doc that we limit to gen1 unless this is specified as gen2 capable - move property to imx6 pcie phy instead of designware core - don't use &ret as temp storage as of_property_read_u32() doesn't change the outval if property isn't found v2: - moved dt property to designware core Signed-off-by: Tim Harvey --- .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 ++++ drivers/pci/host/pci-imx6.c | 24 +++++++++++++++------- 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 3be80c6..b92fafb 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -19,6 +19,10 @@ Optional properties: - fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20 - fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127 - fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127 +- fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for + gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs + do not meet gen2 jitter requirements and thus for gen2 capability a gen2 + compliant clock generator should be used and configured. Example: diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index eb5a275..60a14b8 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -44,6 +44,7 @@ struct imx6_pcie { u32 tx_deemph_gen2_6db; u32 tx_swing_full; u32 tx_swing_low; + int link_gen; }; /* PCIe Root Complex registers (memory-mapped) */ @@ -417,11 +418,15 @@ static int imx6_pcie_establish_link(struct pcie_port *pp) goto err_reset_phy; } - /* Allow Gen2 mode after the link is up. */ - tmp = readl(pp->dbi_base + PCIE_RC_LCR); - tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; - tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; - writel(tmp, pp->dbi_base + PCIE_RC_LCR); + if (imx6_pcie->link_gen == 2) { + /* Allow Gen2 mode after the link is up. */ + tmp = readl(pp->dbi_base + PCIE_RC_LCR); + tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; + tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; + writel(tmp, pp->dbi_base + PCIE_RC_LCR); + } else { + dev_info(pp->dev, "Link: Gen2 disabled\n"); + } /* * Start Directed Speed Change so the best possible speed both link @@ -445,8 +450,7 @@ static int imx6_pcie_establish_link(struct pcie_port *pp) } tmp = readl(pp->dbi_base + PCIE_RC_LCSR); - dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf); - + dev_info(pp->dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); return 0; err_reset_phy: @@ -598,6 +602,12 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) &imx6_pcie->tx_swing_low)) imx6_pcie->tx_swing_low = 127; + /* Limit link speed */ + ret = of_property_read_u32(pp->dev->of_node, "fsl,max-link-speed", + &imx6_pcie->link_gen); + if (ret) + imx6_pcie->link_gen = 1; + ret = imx6_add_pcie_port(pp, pdev); if (ret < 0) return ret;