From patchwork Fri Apr 8 16:13:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 8784421 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1F1C9C0553 for ; Fri, 8 Apr 2016 16:13:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 35497202E9 for ; Fri, 8 Apr 2016 16:13:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2D169202DD for ; Fri, 8 Apr 2016 16:13:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754413AbcDHQNT (ORCPT ); Fri, 8 Apr 2016 12:13:19 -0400 Received: from mail-wm0-f52.google.com ([74.125.82.52]:34530 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754126AbcDHQNS (ORCPT ); Fri, 8 Apr 2016 12:13:18 -0400 Received: by mail-wm0-f52.google.com with SMTP id l6so70654262wml.1; Fri, 08 Apr 2016 09:13:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=nL8z5TwMnA6ffjOh30j2GylogSCxJV2cF73iXgGxWB4=; b=VEttwvJarL0VFjUwDaMAYuzbRhVjJ22fWWp4Jd3rHdfNwh4XLq2G6MboUqbRdyUC9q PlZjHg6xGdTCUF0YWapbnnTIuJsnYZFf/RkuyuIGDNf6pUu+cU3Sl/Vni5fWzKfPkqeE uhtrF62KSx3kD/cU9dEKFG5pimcLYsLjhBOaPuPW2J7NA18F5tXCFxyxsOoie13oCaDg p0mOXHAW8e72bM1bVs1Jkc3hIsVDD1KXjYNBZzZ0CRJ3U/hsJOKXSJfO3Yybo4NVfg3c m0g59XgNsf38loyHVcqRCraw/gxOmM1lObxwIGhD3fk6qru+UoHWrSe7dXPYgdqcCL46 IgSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=nL8z5TwMnA6ffjOh30j2GylogSCxJV2cF73iXgGxWB4=; b=akh89IeUmLBuz6dvuYn+53TK7yOMWAqAsirsdx8Tp5n5ApYjSC4/bSR3EM/CmuO3qV fE03wj2Ym9ytq+z4rmGyM8PGTSqQgJdJae0Q/hcTOwmPcCPssZj60W3DGQT6MrFIsxxX GBZBttD6eJXz39muwREidk3HGB183a6gQI2EP+UtPpPmzATxrk/sjDBqciRoROtXNTE5 GSNzCbdght/d3sozRKIe1RKCjXBTfPAtPKKKTkBHVQHJvG+/inzVpvAPV2XJq7c4VTrk /klT5vtjxGm+QdsfaZ5fNHxIjsivvyCHc2J1wAasmUi9EutMfubELtCGI5y+V3v5FGiD JvDA== X-Gm-Message-State: AD7BkJInGxdDNzLRz4ivh8Qk4TtNjkppkCtoAy2qenxLvDALeD11Huqeu/+WQLL05cZFzg== X-Received: by 10.28.105.5 with SMTP id e5mr4894301wmc.87.1460131996269; Fri, 08 Apr 2016 09:13:16 -0700 (PDT) Received: from localhost (port-19498.pppoe.wtnet.de. [46.59.137.204]) by smtp.gmail.com with ESMTPSA id i5sm14074837wja.23.2016.04.08.09.13.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Apr 2016 09:13:15 -0700 (PDT) From: Thierry Reding To: Bjorn Helgaas Cc: Stephen Warren , Alexandre Courbot , linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 1/2] dt-bindings: pci: tegra: Update for per-lane PHYs Date: Fri, 8 Apr 2016 18:13:13 +0200 Message-Id: <1460131994-24493-1-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.8.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_WEB, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thierry Reding Changes to the pad controller device tree binding have required that each lane be associated with a separate PHY. Update the PCI host bridge device tree binding to allow each root port to define the list of PHYs required to drive the lanes associated with it. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Changes in v4: - add additional lanes subnode when dereferencing PHYs from the XUSB pad controller to reflect changes in its binding .../devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index 75321ae23c08..f5364084b494 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -60,11 +60,14 @@ Required properties: - afi - pcie_x -Required properties on Tegra124 and later: +Required properties on Tegra124 and later (deprecated): - phys: Must contain an entry for each entry in phy-names. - phy-names: Must include the following entries: - pcie +These properties are deprecated in favour of per-lane PHYs define in each of +the root ports (see below). + Power supplies for Tegra20: - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. @@ -122,6 +125,13 @@ Required properties: - Root port 0 uses 4 lanes, root port 1 is unused. - Both root ports use 2 lanes. +Required properties for Tegra124 and later: +- phys: Must contain an phandle to a PHY for each entry in phy-names. +- phy-names: Must include an entry for each active lane. Note that the number + of entries does not have to (though usually will) be equal to the specified + number of lanes in the nvidia,num-lanes property. Entries are of the form + "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes. + Example: SoC DTSI: @@ -169,6 +179,9 @@ SoC DTSI: ranges; nvidia,num-lanes = <2>; + + phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-4}>; + phy-names = "pcie-0"; }; pci@2,0 { @@ -183,6 +196,9 @@ SoC DTSI: ranges; nvidia,num-lanes = <2>; + + phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-2}>; + phy-names = "pcie-0"; }; };