From patchwork Wed Jun 1 12:31:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 9147287 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 458B960757 for ; Wed, 1 Jun 2016 12:32:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 37DB420093 for ; Wed, 1 Jun 2016 12:32:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2C492269DA; Wed, 1 Jun 2016 12:32:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B23E720093 for ; Wed, 1 Jun 2016 12:32:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757834AbcFAMcX (ORCPT ); Wed, 1 Jun 2016 08:32:23 -0400 Received: from mout.kundenserver.de ([217.72.192.73]:55976 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750822AbcFAMcW (ORCPT ); Wed, 1 Jun 2016 08:32:22 -0400 Received: from wuerfel.lan. ([78.42.132.4]) by mrelayeu.kundenserver.de (mreue102) with ESMTPA (Nemesis) id 0MMF1Z-1b9Rgn1VNN-007zhr; Wed, 01 Jun 2016 14:31:40 +0200 From: Arnd Bergmann To: Bjorn Helgaas Cc: Heiko Stuebner , Wenrui Li , Doug Anderson , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Shawn Lin , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Jingoo Han , Pratyush Anand , Arnd Bergmann , Hannes Reinecke , Alex Williamson Subject: [PATCH 1/3] pci: introduce read_bridge/write_bridge pci ops Date: Wed, 1 Jun 2016 14:31:22 +0200 Message-Id: <1464784332-3775650-1-git-send-email-arnd@arndb.de> X-Mailer: git-send-email 2.7.0 X-Provags-ID: V03:K0:qPwrFNAHQH1kgefT9t2KiEI77Co0M8t5FZ7Q+a1XHpwd52lZVI/ VyKVnJ17r1OWNzO+MA9rpHO6IXtmgd/EsPyhRRSzozUglkIjCm/t+mrs6eIEcSBkFRnYZma WkP1HjkE3Q4jVVUxzJs209TZ7E1ARLIOgpWPEzszImX0BbiMn/WBlG0yTlURFfCBumiHZDn TD7NPiRpCGONr327BLysA== X-UI-Out-Filterresults: notjunk:1; V01:K0:uPRHu++XmaI=:+g21yn/KiwY0/UShdH1Riz ZkVhvrtDjvZ6ovVUny7t2fHM7gWvEhaz18159iTWAhR7wMtB4SWkA71zFXA/draHfq/r0jvHY XChPFlzmm1luH+tKWCu0izLp36Li9Vx4daEdMjuYzt1qLGta/E6w9+9/+szYB/MN+NQ9+dH+k GUip43z12wqMl7AD9VoFYJcrfstkjpWiJJjZ31QEQSClS77N0lV9Iz+0fGNrkPSwXSuMHBLBJ agqBFo0NtMqzNM0+odGneFTqfQE+BLJjkskW3rOYYFxy8EYZXNiL+G2kpgxfaF8tMIdbDpRRX 81IU6DNlJd+wlDZNuLYv/vhBerX1mUH0MdJrtMft8Y85UOjtm6WHxdbgH+zDdiwmnsa+QMG8G Ckh7HIssdxTVgDfOlDIx+tDOyss5rke9xsEM999V1J02XCX66m/qIpAhZTI5oMulXMiUuGO3f lmklawQdu8GrCuR71/S+Caq3sran/NtFkfkvAFvZITTjwfY7IWRcFtks1ty2r3dDthRf1ykFQ 6DydP+dZ1AwDmtAbn+FTuingrrremQFIIt/Ed8MyCK0KIGrNl001LC6c4xo7r3SIlZariafPk JJpN+dvlLtrIBFWRoc69cTXM3f6FA91S78sjgSJKUxyZT765SG+bUZsHaVUk/A/V6dhi9E+Hx 6TV+ODmOfyHj3iQ8QeVcsUMQFI+QY0BiD6B/+swzVZbaDvjU5/dVqXWAi9DkmiELC/zM= Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A lot of PCI host bridges require different methods for initiating type 0 and type 1 config space accesses, leading to duplication of code. This adds support for the two different kinds at the pci_ops level, with the newly added map_bridge/read_bridge/write_bridge operations for type 1 accesses. When these are not set, we fall back to the regular map_bus/read/write operations, so all existing drivers keep working, and bridges that have identical operations continue to only require one set. In most cases, a driver will only have to override either map_bridge or read_bridge/write_bridge but not both. Signed-off-by: Arnd Bergmann --- This is slightly refined over what I had in the "Add PCIe driver for Rockchip Soc" thread earlier, but probably not the final version yet, so I'd like to get more feedback on it. In particular, I think it may be useful to add a third set of functions for the config space of devices that are directly attached to the host bridge, as those are sometimes (designware, rcar, mvebu) yet again different from the host bridge itself and from all other devices. On the other hand, that adds further complexity that we may want to leave out of the common code, and I honestly can't seem to come up for a catchy name form the callbacks. drivers/pci/access.c | 35 +++++++++++++++++++++++++++-------- include/linux/pci.h | 3 +++ 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/pci/access.c b/drivers/pci/access.c index d11cdbb8fba3..263606ece211 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c @@ -34,9 +34,12 @@ int pci_bus_read_config_##size \ u32 data = 0; \ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ raw_spin_lock_irqsave(&pci_lock, flags); \ - res = bus->ops->read(bus, devfn, pos, len, &data); \ + if (!bus->parent == 0 && bus->ops->read_bridge) \ + res = bus->ops->read_bridge(bus, devfn, pos, len, &data); \ + else \ + res = bus->ops->read(bus, devfn, pos, len, &data); \ *value = (type)data; \ - raw_spin_unlock_irqrestore(&pci_lock, flags); \ + raw_spin_unlock_irqrestore(&pci_lock, flags); \ return res; \ } @@ -48,8 +51,11 @@ int pci_bus_write_config_##size \ unsigned long flags; \ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ raw_spin_lock_irqsave(&pci_lock, flags); \ - res = bus->ops->write(bus, devfn, pos, len, value); \ - raw_spin_unlock_irqrestore(&pci_lock, flags); \ + if (!bus->parent && bus->ops->write_bridge) \ + res = bus->ops->write_bridge(bus, devfn, pos, len, value);\ + else \ + res = bus->ops->write(bus, devfn, pos, len, value); \ + raw_spin_unlock_irqrestore(&pci_lock, flags); \ return res; \ } @@ -72,7 +78,11 @@ int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, { void __iomem *addr; - addr = bus->ops->map_bus(bus, devfn, where); + if (!bus->parent && bus->ops->map_bridge) + addr = bus->ops->map_bridge(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where); + if (!addr) { *val = ~0; return PCIBIOS_DEVICE_NOT_FOUND; @@ -94,7 +104,10 @@ int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, { void __iomem *addr; - addr = bus->ops->map_bus(bus, devfn, where); + if (!bus->parent && bus->ops->map_bridge) + addr = bus->ops->map_bridge(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where); if (!addr) return PCIBIOS_DEVICE_NOT_FOUND; @@ -114,7 +127,10 @@ int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, { void __iomem *addr; - addr = bus->ops->map_bus(bus, devfn, where & ~0x3); + if (!bus->parent && bus->ops->map_bridge) + addr = bus->ops->map_bridge(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where & ~0x3); if (!addr) { *val = ~0; return PCIBIOS_DEVICE_NOT_FOUND; @@ -135,7 +151,10 @@ int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, void __iomem *addr; u32 mask, tmp; - addr = bus->ops->map_bus(bus, devfn, where & ~0x3); + if (!bus->parent && bus->ops->map_bridge) + addr = bus->ops->map_bridge(bus, devfn, where); + else + addr = bus->ops->map_bus(bus, devfn, where & ~0x3); if (!addr) return PCIBIOS_DEVICE_NOT_FOUND; diff --git a/include/linux/pci.h b/include/linux/pci.h index df41c4645911..2b1d08771b36 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -580,6 +580,9 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); + void __iomem *(*map_bridge)(struct pci_bus *bus, unsigned int devfn, int where); + int (*read_bridge)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); + int (*write_bridge)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); }; /*