From patchwork Fri Jun 10 19:55:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 9170351 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 201F16048F for ; Fri, 10 Jun 2016 19:57:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1121A282F9 for ; Fri, 10 Jun 2016 19:57:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 057102833F; Fri, 10 Jun 2016 19:57:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A7505282F9 for ; Fri, 10 Jun 2016 19:56:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932525AbcFJT44 (ORCPT ); Fri, 10 Jun 2016 15:56:56 -0400 Received: from mail-lf0-f53.google.com ([209.85.215.53]:34485 "EHLO mail-lf0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753180AbcFJT4J (ORCPT ); Fri, 10 Jun 2016 15:56:09 -0400 Received: by mail-lf0-f53.google.com with SMTP id j7so28544463lfg.1 for ; Fri, 10 Jun 2016 12:56:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qMZOCxPM1XtkUNk+SAT+VsI59rVzhSEfxMJH7RE+e9c=; b=O13DCz6BY3eCF1qFFx3CnxzVnbUERrR8OBZvTf/wlKA/nTKMAiy4AdozoLG+KCc+lt fBeEZztVYXRQapj/jB3Msm6XNKAlHBasqvjj8omjpb1F77E2/ONONzkCid95aun/50Ec dXEzGJVhGnOmfhax/pMOVIXL5BCrtFvrTGcGIWDsgt4xkaxJi8Xcjjm5DTejdz0kN/Aw Efmny8L43BhKa3E0mzn7JC7tyn+uOI5CXqlixK7VzzYwgKSmxJiGZDoKLR48K+ur0juT mTEdfsoH/KDz+dJgR4m8EBwJu7W4737VM5V5x+DaTYb/0of6E4kmSDeTFYH4M2e3U2Lc ZsKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qMZOCxPM1XtkUNk+SAT+VsI59rVzhSEfxMJH7RE+e9c=; b=ZW7EsEuafCP35KGmWr95mKeZ7T2+fwb4tXLR7Hm02At/+bonIF0t8jj50s0jVV6Nb5 mpH5qlwATlRlCbLebuBAPSIAnY9ZN4G/Bhi+gXnK/4wD0PhTbh/O2JLZ5pQUb6MexmQn fF5yxVIuprppennpoN+8djYLpDuau8tov2zFsnNOfcRqbpsUO987nnmhlug3XyEC49g0 AC5BaayNJ1uEaifcB4/RpFf9qnsU2FSFWq/iqTb9F0u7NwW4BPeHACqCftXGCoaUtwYQ utQ6i83quT77Zecw3ubagN5b/Ewjwx1O246MstqfxgG/3YlP/boUlSyuQuFB4IHMTBuv nN8Q== X-Gm-Message-State: ALyK8tJHUjBn7tZKgSzrDrISPRDJNd6ZeXa3kwldfMhta8QrI0E1bE2tBiol2M99Q8UFuw== X-Received: by 10.25.90.15 with SMTP id o15mr1163511lfb.67.1465588567300; Fri, 10 Jun 2016 12:56:07 -0700 (PDT) Received: from tn-HP-4.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id a190sm1377175lfe.21.2016.06.10.12.56.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 10 Jun 2016 12:56:06 -0700 (PDT) From: Tomasz Nowicki To: helgaas@kernel.org, arnd@arndb.de, will.deacon@arm.com, catalin.marinas@arm.com, rafael@kernel.org, hanjun.guo@linaro.org, Lorenzo.Pieralisi@arm.com, okaya@codeaurora.org, jchandra@broadcom.com Cc: robert.richter@caviumnetworks.com, mw@semihalf.com, Liviu.Dudau@arm.com, ddaney@caviumnetworks.com, wangyijing@huawei.com, Suravee.Suthikulpanit@amd.com, msalter@redhat.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org, jcm@redhat.com, andrea.gallo@linaro.org, dhdang@apm.com, jeremy.linton@arm.com, liudongdong3@huawei.com, cov@codeaurora.org, Tomasz Nowicki Subject: [PATCH V9 10/11] ARM64/PCI: Implement ACPI low-level calls to access PCI_Config region from AML Date: Fri, 10 Jun 2016 21:55:18 +0200 Message-Id: <1465588519-11334-11-git-send-email-tn@semihalf.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465588519-11334-1-git-send-email-tn@semihalf.com> References: <1465588519-11334-1-git-send-email-tn@semihalf.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ACPI spec6.1 - chapter: 5.5.2.4 defines OperationRegion (Declare Operation Region). Following the spec: " [...] An Operation Region is a specific region of operation within an address space that is declared as a subset of the entire address space using a starting address (offset) and a length. Control methods must have exclusive access to any address accessed via fields declared in Operation Regions. [...]". OperationRegion allows to declare various of operation region address space identifiers including PCI_Config. PCI_Config is meant to access PCI configuration space from the ASL. So every time ASL opcode operates on PCI_Config space region, ASL interpreter dispatches accesses to OS low-level calls - raw_pci_write() and raw_pci_read() for Linux - so-called ACPI RAW accessors. In order to support PCI_Config operation region, implement mentioned raw_pci_write() and raw_pci_read() calls so they find associated bus and call read/write ops. Waiting for clarification in the ACPI specifications in relation to PCI_Config space handling before PCI bus enumeration is completed, current code does not support PCI_Config region accesses before PCI bus enumeration whilst providing full AML PCI_Config access availability when the PCI bus enumeration is completed by the kernel so that RAW accessors can look-up PCI operations through the struct pci_bus associated with a PCI bus. Signed-off-by: Tomasz Nowicki Signed-off-by: Jayachandran C Reviewed-by: Lorenzo Pieralisi --- arch/arm64/kernel/pci.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index b3b8a2c..328f857 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -71,13 +71,21 @@ int pcibios_alloc_irq(struct pci_dev *dev) int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, int reg, int len, u32 *val) { - return -ENXIO; + struct pci_bus *b = pci_find_bus(domain, bus); + + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->read(b, devfn, reg, len, val); } int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, int reg, int len, u32 val) { - return -ENXIO; + struct pci_bus *b = pci_find_bus(domain, bus); + + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->write(b, devfn, reg, len, val); } #ifdef CONFIG_NUMA