From patchwork Tue Aug 30 10:39:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Kumar Gogada X-Patchwork-Id: 9305287 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1974B607F0 for ; Tue, 30 Aug 2016 12:12:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0A9C928BB4 for ; Tue, 30 Aug 2016 12:12:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F32A528BB8; Tue, 30 Aug 2016 12:12:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EDAAD28BB4 for ; Tue, 30 Aug 2016 12:12:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758457AbcH3MMi (ORCPT ); Tue, 30 Aug 2016 08:12:38 -0400 Received: from mail-bl2nam02on0051.outbound.protection.outlook.com ([104.47.38.51]:1824 "EHLO NAM02-BL2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1758241AbcH3MMh (ORCPT ); Tue, 30 Aug 2016 08:12:37 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector1-xilinx-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=7ZRG2S9lNRN6kWVfSVcIbkEC3VN4hAobyjtuqrMFPc4=; b=OX9/nryEO5SuylWrJQsYQOhTs+dYLGKlXh+HT+bmfnZBEcY0GP4Vd9lZ5Qu7pESt5q66/hVguFogwpeLXtGayGDZvICiRnLT9oUf5JV8KYwKl2ehraLgn15jfX+TwLUSSKLipZNps2G9sQNEcSJr22oJJVSRt3T5CjO1zVGpwZE= Received: from BN6PR02CA0054.namprd02.prod.outlook.com (10.175.94.144) by BY1PR02MB1146.namprd02.prod.outlook.com (10.162.108.148) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA_P384) id 15.1.557.21; Tue, 30 Aug 2016 10:39:53 +0000 Received: from BL2NAM02FT052.eop-nam02.prod.protection.outlook.com (2a01:111:f400:7e46::200) by BN6PR02CA0054.outlook.office365.com (2603:10b6:404:f9::16) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA_P384) id 15.1.587.13 via Frontend Transport; Tue, 30 Aug 2016 10:39:53 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2NAM02FT052.mail.protection.outlook.com (10.152.77.0) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.587.6 via Frontend Transport; Tue, 30 Aug 2016 10:39:53 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1begSN-0004e6-JQ; Tue, 30 Aug 2016 03:39:51 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1begSP-00053C-Aj; Tue, 30 Aug 2016 03:39:53 -0700 Received: from xsj-pvapsmtp01 (mailhub.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u7UAdnga017293; Tue, 30 Aug 2016 03:39:49 -0700 Received: from [172.23.64.217] (helo=xhd-lin64re105.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1begSK-0004zd-KL; Tue, 30 Aug 2016 03:39:48 -0700 Received: by xhd-lin64re105.xilinx.com (Postfix, from userid 45489) id 804A7CA1C3E; Tue, 30 Aug 2016 16:09:47 +0530 (IST) From: Bharat Kumar Gogada To: , , , , , , CC: , , , , Bharat Kumar Gogada Subject: [PATCH 2/3] PCI: Xilinx NWL PCIe: Enabling all MSI interrupts using MSI mask. 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR02MB1146 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The current mask enables and allows only one MSI interrupt on each MSI line. This change, enables all MSI interrupts, which will also support End Points with multi MSI support. Signed-off-by: Bharat Kumar Gogada --- drivers/pci/host/pcie-xilinx-nwl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index 86c1834..d8d43e6 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -120,8 +120,8 @@ MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD) /* MSI interrupt status mask bits */ -#define MSGF_MSI_SR_LO_MASK BIT(0) -#define MSGF_MSI_SR_HI_MASK BIT(0) +#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0) +#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0) #define MSII_PRESENT BIT(0) #define MSII_ENABLE BIT(0)