From patchwork Thu Sep 8 06:25:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "M.h. Lian" X-Patchwork-Id: 9320653 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 479CB6077F for ; Thu, 8 Sep 2016 07:57:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3904F296AD for ; Thu, 8 Sep 2016 07:57:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D765296B1; Thu, 8 Sep 2016 07:57:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6F76A296AD for ; Thu, 8 Sep 2016 07:57:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757655AbcIHH5Z (ORCPT ); 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nxp.com; dkim=none (message not signed) header.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD035.mail.protection.outlook.com (10.58.52.159) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.587.6 via Frontend Transport; Thu, 8 Sep 2016 06:23:58 +0000 Received: from lmh.ap.freescale.net (lmh.ap.freescale.net [10.193.20.63]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id u886No2R022045; Wed, 7 Sep 2016 23:23:54 -0700 From: Minghuan Lian To: CC: , Roy Zang , Mingkai Hu , Stuart Yoder , Yang-Leo Li , Arnd Bergmann , "Bjorn Helgaas" , Jingoo Han , "Minghuan Lian" Subject: [PATCH 2/2] pci/layerscape: fix error response behavior Date: Thu, 8 Sep 2016 14:25:50 +0800 Message-ID: <1473315950-6396-2-git-send-email-Minghuan.Lian@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1473315950-6396-1-git-send-email-Minghuan.Lian@nxp.com> References: <1473315950-6396-1-git-send-email-Minghuan.Lian@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131177894385772383; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR03MB2447 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP By default, when the PCIe controller experiences an erroneous completion from an external completer for its outbound non-posted request, it always sends an OKAY response to the device's internal AXI slave system interface. However, such default system error response behavior cannot be used for other types of outbound non-posted requests. For example, the outbound memory read transaction requires an actual ERROR response, like UR completion or completion timeout. The patch is to fix it by forwarding the error response of the non-posted request. Signed-off-by: Minghuan Lian --- drivers/pci/host/pci-layerscape.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index cf783ad..873447a 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -34,6 +34,8 @@ /* PEX Internal Configuration Registers */ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ #define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ +#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */ +#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */ /* PEX LUT registers */ #define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */ @@ -99,6 +101,12 @@ static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) dw_pcie_disable_outbound_atu(&pcie->pp, i); } +/* Forward error response of outbound non-posted requests */ +static void ls_pcie_fix_error_response(struct ls_pcie *pcie) +{ + iowrite32(PCIE_ABSERR_SETTING, pcie->dbi + PCIE_ABSERR); +} + static int ls1021_pcie_link_up(struct pcie_port *pp) { u32 state; @@ -166,6 +174,7 @@ static void ls_pcie_host_init(struct pcie_port *pp) iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); ls_pcie_disable_outbound_atus(pcie); + ls_pcie_fix_error_response(pcie); } static int ls_pcie_msi_host_init(struct pcie_port *pp,