From patchwork Thu Jan 12 06:28:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongdong Liu X-Patchwork-Id: 9512173 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 47430601E5 for ; Thu, 12 Jan 2017 06:13:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3877F28638 for ; Thu, 12 Jan 2017 06:13:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2CE0228634; Thu, 12 Jan 2017 06:13:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2F3528634 for ; Thu, 12 Jan 2017 06:13:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750768AbdALGN3 (ORCPT ); Thu, 12 Jan 2017 01:13:29 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:53227 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750762AbdALGN2 (ORCPT ); Thu, 12 Jan 2017 01:13:28 -0500 Received: from 172.24.1.136 (EHLO szxeml422-hub.china.huawei.com) ([172.24.1.136]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DXT01781; Thu, 12 Jan 2017 14:13:19 +0800 (CST) Received: from linux-ioko.site (10.71.200.31) by szxeml422-hub.china.huawei.com (10.82.67.152) with Microsoft SMTP Server id 14.3.235.1; Thu, 12 Jan 2017 14:13:09 +0800 From: Dongdong Liu To: CC: , , , , , Dongdong Liu Subject: [PATCH 1/3] PCI:hisi: Add DT almost ECAM support for HiSilicon Hip06/Hip07 host controllers Date: Thu, 12 Jan 2017 14:28:22 +0800 Message-ID: <1484202504-96686-2-git-send-email-liudongdong3@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1484202504-96686-1-git-send-email-liudongdong3@huawei.com> References: <1484202504-96686-1-git-send-email-liudongdong3@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.71.200.31] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.58771E80.0410, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: bafe93549adc1f738bac7a6ff328e74d Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PCIe controller in Hip06/Hip07 SoCs is not completely ECAM-compliant. It is non-ECAM only for the RC bus config space; for any other bus underneath the root bus it does support ECAM access. This is to add the almost ECAM support in DT way. Signed-off-by: Dongdong Liu Reviewed-by: Gabriele Paoloni Reviewed-by: Zhou Wang --- .../devicetree/bindings/pci/hisilicon-pcie.txt | 37 +++++++++++++++ drivers/pci/host/pcie-hisi.c | 54 ++++++++++++++++++++-- 2 files changed, 88 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index 59c2f47..38e6dc3 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -42,3 +42,40 @@ Hip05 Example (note that Hip06 is the same except compatible): 0x0 0 0 4 &mbigen_pcie 4 13>; status = "ok"; }; + +HiSilicon Hip06/Hip07 PCIe host bridge DT (almost ecam) description +The properties and their meanings are identical to those described in +host-generic-pci.txt except as listed below. + +Properties of the host controller node that differ from +host-generic-pci.txt: + +- compatible : Must be "hisilicon,pcie-almost-ecam" + +- reg : Two entries: First the ECAM configuration space for any + other bus underneath the root bus. Second, the base + and size of the HiSilicon host bridge registers inculde + the RC itself config space. + +Example: + pcie0: pcie@a0090000 { + compatible = "hisilicon,pcie-almost-ecam"; + reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */ + <0 0xa0090000 0 0x10000>; /* host bridge registers */ + bus-range = <0 31>; + msi-map = <0x0000 &its_dsa 0x0000 0x2000>; + msi-map-mask = <0xffff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000 + 0x01000000 0 0 0 0xb7ff0000 0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 + 0x0 0 0 2 &mbigen_pcie0 650 4 + 0x0 0 0 3 &mbigen_pcie0 650 4 + 0x0 0 0 4 &mbigen_pcie0 650 4>; + status = "ok"; + }; diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c index a301a71..f37f5a2 100644 --- a/drivers/pci/host/pcie-hisi.c +++ b/drivers/pci/host/pcie-hisi.c @@ -24,7 +24,7 @@ #include #include "../pci.h" -#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) +#if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) @@ -74,6 +74,8 @@ static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, return pci_ecam_map_bus(bus, devfn, where); } +#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) + static int hisi_pcie_init(struct pci_config_window *cfg) { struct device *dev = cfg->parent; @@ -262,17 +264,23 @@ static int hisi_pcie_probe(struct platform_device *pdev) const struct of_device_id *match; struct resource *reg; struct device_driver *driver; + struct pci_ecam_ops *ops; int ret; + driver = dev->driver; + match = of_match_device(driver->of_match_table, dev); + if (!strcmp(match->compatible, "hisilicon,pcie-almost-ecam")) { + ops = (struct pci_ecam_ops *)match->data; + return pci_host_common_probe(pdev, ops); + } + hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL); if (!hisi_pcie) return -ENOMEM; pp = &hisi_pcie->pp; pp->dev = dev; - driver = dev->driver; - match = of_match_device(driver->of_match_table, dev); hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data; hisi_pcie->subctrl = @@ -302,6 +310,40 @@ static int hisi_pcie_probe(struct platform_device *pdev) &hisi_pcie_link_up_hip06 }; +static int hisi_pcie_platform_init(struct pci_config_window *cfg) +{ + struct device *dev = cfg->parent; + struct platform_device *pdev = to_platform_device(dev); + struct resource *res; + void __iomem *reg_base; + + if (!dev->of_node) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(dev, "missing \"reg[1]\"property\n"); + return -EINVAL; + } + + reg_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!reg_base) + return -ENOMEM; + + cfg->priv = reg_base; + return 0; +} + +struct pci_ecam_ops hisi_pcie_platform_ops = { + .bus_shift = 20, + .init = hisi_pcie_platform_init, + .pci_ops = { + .map_bus = hisi_pcie_map_bus, + .read = hisi_pcie_acpi_rd_conf, + .write = hisi_pcie_acpi_wr_conf, + } +}; + static const struct of_device_id hisi_pcie_of_match[] = { { .compatible = "hisilicon,hip05-pcie", @@ -311,6 +353,11 @@ static int hisi_pcie_probe(struct platform_device *pdev) .compatible = "hisilicon,hip06-pcie", .data = (void *) &hip06_ops, }, + + { + .compatible = "hisilicon,pcie-almost-ecam", + .data = (void *) &hisi_pcie_platform_ops, + }, {}, }; @@ -324,3 +371,4 @@ static int hisi_pcie_probe(struct platform_device *pdev) builtin_platform_driver(hisi_pcie_driver); #endif +#endif